Opensource DDR3 Controller
-
Updated
Jan 18, 2026 - Verilog
#
memory-controller
Here are 19 public repositories matching this topic...
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
-
Updated
Dec 1, 2022 - Verilog
mirror of https://git.elphel.com/Elphel/eddr3
-
Updated
Oct 16, 2017 - Verilog
This is not Linux kernel maintainer's tree, but an open-source work in progress. Officially maintained repositories are under kernel.org (Samsung SoC, memory controller drivers etc.).
linux arm kernel linux-kernel tesla armv7 samsung odroid arm64 devicetree snapdragon qualcomm armv8 exynos fsd qcom memory-controller samsung-soc gs101 gs201
-
Updated
May 15, 2026 - C
A bare-metal SRAM memory controller suitable for Xilinx FPGAs.
-
Updated
Jan 15, 2024 - Verilog
Multi-Channel DDR Memory Controller Design with BFM-Based Verification and UVM-Style Testbench
-
Updated
Feb 23, 2026 - Verilog
🛠 A SDRAM controller in Verilog HDL
-
Updated
Mar 21, 2022 - Verilog
This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.
-
Updated
Feb 16, 2026 - SystemVerilog
The Enhanced SRAM Controller handles secure, efficient memory operations with features like burst mode, error correction, power-saving, and clock domain crossing. It’s perfect for applications requiring robust and reliable memory handling.
memory verilog sram memory-management vivado questasim sdram sdram-controller memory-controller verilog-project vlsi-design sram-controller sram-controller-advanced sram-features-power-security-brust verlog-hdl enhanched-sram-controller
-
Updated
Oct 21, 2024 - Verilog
SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.
python tcl verification rtl scoreboard sram regression-testing systemverilog modelsim uvm testbench constrained-random memory-controller questa hardware-verification functional-coverage uvm-verification directed-testing design-verification-project
-
Updated
May 14, 2026 - SystemVerilog
This repository contains a JEDEC-style DDR2 SDRAM controller targeting the memory devices. The controller exposes a simple FIFO-like front-end interface and maps host commands into DDR2 transactions, including full power-up initialization, periodic refresh, scalar and block reads/writes, and DQS-based data capture.
-
Updated
Feb 15, 2026 - Verilog
Behavioral architecture of a read/write cycle controller for a DRAM chip.
-
Updated
May 26, 2023 - VHDL
DDR memory controller implementation and verification
-
Updated
Oct 6, 2025
Advanced SRAM Controller with ECC Support for Sky130 Process - Production-Ready Multi-Port Memory System.
fpga verification pytest systemverilog open-source-hardware cocotb memory-controller vlsi-design sram-controller asic-design ecc-memory sky130 multi-port-memory
-
Updated
Aug 8, 2025 - Python
In this repository, I have published my knowledge gained while working on FIFO Project implementation using Verilog, System Verilog, UVM
-
Updated
Dec 3, 2024 - SystemVerilog
Redesign of 'vga_src' video card architcture using proper FIFOs
-
Updated
Mar 31, 2025 - Verilog
Built a custom ALU in Verilog with arithmetic, logic, shift, comparison, and exception handling operations, and verified functionality using a self-checking testbench.
-
Updated
Apr 18, 2026 - Verilog
This project is a course based see SEC/term 7/Computer Architecture
-
Updated
Dec 9, 2025 - Verilog
Improve this page
Add a description, image, and links to the memory-controller topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the memory-controller topic, visit your repo's landing page and select "manage topics."