GitHub - amirah-sri/all_verilog: I am trying to develop my skills through daily practice and consistency.

Name		Name	Last commit message	Last commit date
Latest commit History 67 Commits
SIMULATED RESULTS		SIMULATED RESULTS
TEST BENCH		TEST BENCH
final_interleaver		final_interleaver
integrated_scrambler_descrambler		integrated_scrambler_descrambler
interleaver		interleaver
15_bit_scrambler.v		15_bit_scrambler.v
IHC.v		IHC.v
THC.v		THC.v
THC_decoder.v		THC_decoder.v
mod_12_counter.v		mod_12_counter.v
scrambler_1.v		scrambler_1.v
scrambler_descrambler.v		scrambler_descrambler.v