Complete-ASIC-Flow-of-I2C-communication-protocol

This Repository contains the Complete ASIC Flow of I2C communication protocol

Overview

This project aims to design and implement a complete layout (GDS) of the I2C communication protocol using SAED90_EDK. I2C, or Inter-Integrated Circuit, is a bi-directional serial bus that facilitates efficient data exchange between devices. It is particularly well-suited for applications requiring intermittent communication over short distances among multiple devices.

Key Features:

• I2C is characterized by its simplicity and efficiency, making it a preferred choice for various embedded systems.
• The protocol supports multi-master functionality, enabling multiple devices to communicate on the same bus. Collision detection and arbitration mechanisms prevent data corruption during simultaneous bus access by multiple masters.
• SAED90_EDK will be utilized for the ASIC flow, encompassing various stages such as RTL design, synthesis, place and route, and layout generation.
• Through this project, a comprehensive understanding of the I2C protocol and ASIC design flow will be developed, laying the foundation for creating robust and efficient communication interfaces in future semiconductor designs.

This project not only offers practical experience in ASIC design but also contributes to enhancing knowledge and skills in implementing industry-standard communication protocols for embedded systems.

This project also utilizes a comprehensive set of EDA tools, including Synopsys Design Compiler (DC) for logic synthesis, Synopsys Formality for formal verification, Synopsys IC Compiler II Library Manager for data setup and dlib creation, Synopsys IC Compiler II for back-end flow, and Synopsys PrimeTime for static timing analysis.

Internal structure of I2C

Synthesis Stage

• Schematic view of Synthesis netlist

• Synthesis Output files

Formal Verification

• Result of Formal Verification

• Formal Verification reports

Floor planning

Power planning

Placement

Clock tree synthesis (CTS)

• With Power Network

• 

• Without Power Network

• 

Routing

• Before Routing Optimization

• • Without Power Network

  • 

• • With Power Network

  • 

• After Routing Optimization

• • Without Power Network

  • 

• • With Power Network

  • 

Placing Filler cells

• With Power Network

• 

• Without Power Network

• 

• After removing Fillers with violation

• 

Global Route Congestion map

• 

Pin Density map

• 

Power Density map

• 

Cell Density map

• 

PNA Voltage drop map

• 

Back-end reports

• 

ICC II output files

• 

PrimeTime Histogram

• 

PrimeTime Reports

• 

Final Layout View of the design

•