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Copy file name to clipboardExpand all lines: IDE/Renesas/e2studio/RZN2L/README.md
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@@ -10,7 +10,7 @@ They also include benchmark and cryptography tests for the wolfCrypt library.
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The example project contains both the wolfSSL and wolfCrypt libraries.
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It is built as a `Renesas RZ/N C/C++ FSP Project` and contains the Renesas RZ
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configuration. The wolfssl project uses `Renesas Secure IP on RZ`
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as hardware acceleration for cyptography.
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as hardware acceleration for cryptography.
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**Limitation**
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|Item|Name/Version|
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|:--|:--|
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|Board|RZN2L|
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|Device|R9A07G084M04GBG|
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|Device|R9A07G084M08GBG|
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|Toolchain|GCC for Renesas RZ|
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|Toolchain Version|10.3.1.20210824|
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|FSP Version|1.2.0|
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|Board Support Package Common Files|v1.20||
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|I/O Port|v1.2.0||
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|Arm CMSIS Version 5 - Core (M)|v5.7.0+renesas.1||
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|Board support package for R9A07G084M04GBG|v1.2.0||
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|Board support package for R9A07G084M04GBG|v1.2.0|Note1|
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|Board support package for RZN2L|v1.2.0||
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|Board support package for RZN2L - FSP Data|v1.2.0||
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|RSK+RZN2L Board Support Files (RAM execution without flash memory)|v1.2.0||
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|Renesas Secure IP Driver|v1.3.0+fsp.1.2.0|Need to contact Renesas to get RSIP module|
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|RSIP Engine for RZ/N2L|v1.3.0+fsp.1.2.0|Need to contact Renesas to get RSIP module|
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Note1:\
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To use RSIP driver, a device type should be `R9A07G084M04GBG`. However, choosing `R9A07G084M04GBG` won't allow to select `RSK+RZN2L` board. This example uses LED and external flash memory on `RSK + RZN2L` board. Therefore, the example temporary `R9A07G084M04GBG` for the device type. Updating e2studio or fsp could resolve the issue.
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## Setup Steps and Build wolfSSL Library
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|Thread Symbol|rzn2l_tst_thread|
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|Thread Name|rzn2l_tst_thread|
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|Thread Stack size|increase depending on your environment<br> e.g. 0xA000|
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|Thread MemoryAllocation|Dyamic|
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|Thread MemoryAllocation|Dynamic|
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|Common General Use Mutexes|Enabled|
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|Common General Enable Backward Compatibility|Enabled|
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|Common Memory Allocation Support Dynamic Allocation|Enabled|
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3.) Prepare UART to logging
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+ Download Sample package from [BACnet Start-Up](https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/bacnet-start-rzn2l-rsk)
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+ Copy the following C source files from the project to src/serial_io folder of `test_RZN2L`
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+ um_serial_io_uart.c
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+ um_serial_io_task_writer.c
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+ um_serial_io_cfg.h
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+ um_common_api.h
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+ um_common_cfg.h
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+ um_serial_io.c
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+ um_serial_io.h
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+ um_serial_io_api.h
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+ um_serial_io_internal.h
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+ Copy the following C source files from the project to src/serial_io folder of `test_RZN2L`\
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um_serial_io_uart.c\
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um_serial_io_task_writer.c\
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um_serial_io_cfg.h\
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um_common_api.h\
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um_common_cfg.h\
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um_serial_io.c\
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um_serial_io.h\
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um_serial_io_api.h\
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um_serial_io_internal.h
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+ Open um_serial_io_task_writer.c and re-name printf to uart_printf
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3.) Build `test_RZN2L` project
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2). Select J-Link ARM and R9A07G084M04
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3). Break at Entory point. Change `cpsr` register value from 0xXXXXX1yy to 0xXXXXX1da
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3). Break at Entry point. Change `cpsr` register value from 0xXXXXX1yy to 0xXXXXX1da
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## Run TLS 1.3 Client
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1.) Enable `WOLFSSL_TLS13` macro in `user_settings.h`
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```
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**Note**
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`SHA1/224/256/384/512` and `Random generation` of RSIP driver are enabled at the sampele output above while running wolfCrypt test.
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`SHA1/224/256/384/512` and `Random generation` of RSIP driver are enabled at the sample output above while running wolfCrypt test.
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## Run Benchmark
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End wolfCrypt Benchmark
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```
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**Note**
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`SHA1/224/256/384/512` and `Random generation` of RSIP driver are enabled at the sampele output above.
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`SHA1/224/256/384/512` and `Random generation` of RSIP driver are enabled at the sample output above.
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## Support
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For support inquiries and questions, please email support@wolfssl.com. Feel free to reach out to info@wolfssl.jp as well.
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