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svofskisvofski
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fixed smooth scrolling, super happy version
SCAN_7INCH is here to stay for 800x480 lcd panels probably the scrolling fix can be backported to SCAN_5_3 as well, but I don't think it's useful at all because that mode is really hacky
1 parent 8a6fe5b commit 7d2d57c

4 files changed

Lines changed: 126 additions & 120 deletions

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‎project/tangnano9k/vector06cc/vector06cc.gprj‎

Lines changed: 73 additions & 73 deletions
Original file line numberDiff line numberDiff line change
@@ -6,79 +6,79 @@
66
<Device name="GW1NR-9C" pn="GW1NR-LV9QN88PC6/I5">gw1nr9c-004</Device>
77
<FileList>
88
<File path="src/gowin_rpll72/gowin_rpll72.v" type="file.verilog" enable="1"/>
9-
<File path="../../../src/ay/ayglue.v" type="file.verilog" enable="1"/>
10-
<File path="../../../src/border_delay.v" type="file.verilog" enable="1"/>
11-
<File path="../../../src/floppy/dma_rw.v" type="file.verilog" enable="1"/>
12-
<File path="../../../src/floppy/floppy.v" type="file.verilog" enable="0"/>
13-
<File path="../../../src/floppy/floppy_neo430.v" type="file.verilog" enable="1"/>
14-
<File path="../../../src/floppy/neo430/neo430_cpu.v" type="file.verilog" enable="0"/>
15-
<File path="../../../src/floppy/spi.v" type="file.verilog" enable="1"/>
16-
<File path="../../../src/floppy/timer100hz.v" type="file.verilog" enable="1"/>
17-
<File path="../../../src/floppy/upi_uart/uart.v" type="file.verilog" enable="0"/>
18-
<File path="../../../src/floppy/verilog-6502-copy/ALU.v" type="file.verilog" enable="1"/>
19-
<File path="../../../src/floppy/verilog-6502-copy/cpu.v" type="file.verilog" enable="1"/>
20-
<File path="../../../src/floppy/wd1793.v" type="file.verilog" enable="1"/>
21-
<File path="../../../src/i8253/8253.v" type="file.verilog" enable="1"/>
22-
<File path="../../../src/keyboard/keymatrix_ram.v" type="file.verilog" enable="1"/>
23-
<File path="../../../src/keyboard/ps2k.v" type="file.verilog" enable="1"/>
24-
<File path="../../../src/keyboard/scan2matrix.v" type="file.verilog" enable="1"/>
25-
<File path="../../../src/keyboard/vectorkeys.v" type="file.verilog" enable="0"/>
26-
<File path="../../../src/keyboard/vectorkeys2.v" type="file.verilog" enable="1"/>
27-
<File path="../../../src/oneshot.v" type="file.verilog" enable="1"/>
28-
<File path="../../../src/osd/chargen.v" type="file.verilog" enable="0"/>
29-
<File path="../../../src/osd/screenbuffer.v" type="file.verilog" enable="0"/>
30-
<File path="../../../src/osd/textmode.v" type="file.verilog" enable="1"/>
31-
<File path="../../../src/ramdisk/kvaz.v" type="file.verilog" enable="1"/>
32-
<File path="../../../src/specialkeys.v" type="file.verilog" enable="1"/>
33-
<File path="../../../src/tangnano9k/audio/I2C_AV_Config.v" type="file.verilog" enable="0"/>
34-
<File path="../../../src/tangnano9k/audio/I2C_Controller.v" type="file.verilog" enable="0"/>
35-
<File path="../../../src/tangnano9k/audio/audio_io.v" type="file.verilog" enable="1"/>
36-
<File path="../../../src/tangnano9k/blackvideo/VGAMod.v" type="file.verilog" enable="1"/>
37-
<File path="../../../src/tangnano9k/bootrom/bootrom.v" type="file.verilog" enable="1"/>
38-
<File path="../../../src/tangnano9k/clockster.v" type="file.verilog" enable="1"/>
39-
<File path="../../../src/tangnano9k/gowin_rpll48p24/gowin_rpll48p24.v" type="file.verilog" enable="1"/>
40-
<File path="../../../src/tangnano9k/hidkeyboard/hidmatrix.v" type="file.verilog" enable="1"/>
41-
<File path="../../../src/tangnano9k/hidkeyboard/uarthid.v" type="file.verilog" enable="1"/>
42-
<File path="../../../src/tangnano9k/k580vv55.v" type="file.verilog" enable="1"/>
43-
<File path="../../../src/tangnano9k/multikvaz.v" type="file.verilog" enable="1"/>
44-
<File path="../../../src/tangnano9k/palette_ram/palette_ram.v" type="file.verilog" enable="1"/>
45-
<File path="../../../src/tangnano9k/psram/psram_controller.v" type="file.verilog" enable="1"/>
46-
<File path="../../../src/tangnano9k/ram.v" type="file.verilog" enable="1"/>
47-
<File path="../../../src/tangnano9k/rom.v" type="file.verilog" enable="1"/>
48-
<File path="../../../src/tangnano9k/soundcodec.v" type="file.verilog" enable="1"/>
49-
<File path="../../../src/tangnano9k/uart/haltmode.v" type="file.verilog" enable="1"/>
50-
<File path="../../../src/tangnano9k/uart/intelhex_rx.v" type="file.verilog" enable="1"/>
51-
<File path="../../../src/tangnano9k/uart/uart_rx.v" type="file.verilog" enable="1"/>
52-
<File path="../../../src/tangnano9k/uart/uart_tx.v" type="file.verilog" enable="1"/>
53-
<File path="../../../src/tangnano9k/uart/uart_tx_V2.v" type="file.verilog" enable="1"/>
54-
<File path="../../../src/tangnano9k/vector06cc.v" type="file.verilog" enable="1"/>
55-
<File path="../../../src/tangnano9k/vi53/k580vi53.v" type="file.verilog" enable="1"/>
56-
<File path="../../../src/tangnano9k/video/vga_refresh.v" type="file.verilog" enable="1"/>
57-
<File path="../../../src/tangnano9k/video/video.v" type="file.verilog" enable="1"/>
58-
<File path="../../../src/tangnano9k/video/videomod.v" type="file.verilog" enable="1"/>
59-
<File path="../../../src/tangnano9k/vram.v" type="file.verilog" enable="1"/>
60-
<File path="../../../src/video/framebuffer.v" type="file.verilog" enable="1"/>
61-
<File path="../../../src/video/rambuffer.v" type="file.verilog" enable="1"/>
62-
<File path="../../../src/video/shiftreg2.v" type="file.verilog" enable="1"/>
63-
<File path="../../../src/vm80/vm80a.v" type="file.verilog" enable="1"/>
64-
<File path="../../../src/T80/T80.vhd" type="file.vhdl" enable="1"/>
65-
<File path="../../../src/T80/T8080se.vhd" type="file.vhdl" enable="1"/>
66-
<File path="../../../src/T80/T80_ALU.vhd" type="file.vhdl" enable="1"/>
67-
<File path="../../../src/T80/T80_MCode.vhd" type="file.vhdl" enable="1"/>
68-
<File path="../../../src/T80/T80_Pack.vhd" type="file.vhdl" enable="1"/>
69-
<File path="../../../src/T80/T80_Reg.vhd" type="file.vhdl" enable="1"/>
70-
<File path="../../../src/T80/T80sef.vhd" type="file.vhdl" enable="1"/>
71-
<File path="../../../src/ay/ay8910.vhd" type="file.vhdl" enable="1"/>
72-
<File path="../../../src/ay/ym2149.vhd" type="file.vhdl" enable="1"/>
73-
<File path="../../../src/floppy/neo430/core/neo430_addr_gen.vhd" type="file.vhdl" enable="1" library="neo430"/>
74-
<File path="../../../src/floppy/neo430/core/neo430_alu.vhd" type="file.vhdl" enable="1" library="neo430"/>
75-
<File path="../../../src/floppy/neo430/core/neo430_control.vhd" type="file.vhdl" enable="1" library="neo430"/>
76-
<File path="../../../src/floppy/neo430/core/neo430_cpu.vhd" type="file.vhdl" enable="1" library="neo430"/>
77-
<File path="../../../src/floppy/neo430/core/neo430_package.vhd" type="file.vhdl" enable="1" library="neo430"/>
78-
<File path="../../../src/floppy/neo430/core/neo430_reg_file.vhd" type="file.vhdl" enable="1" library="neo430"/>
79-
<File path="../../../src/floppy/neo430/neo430_cpu_std_logic.vhd" type="file.vhdl" enable="1"/>
80-
<File path="../../../src/floppy/uart/txd.vhd" type="file.vhdl" enable="1"/>
81-
<File path="../../../src/i82c55/i82c55.vhd" type="file.vhdl" enable="1"/>
9+
<File path="C:/Gowin/projects/vector06cc/src/ay/ayglue.v" type="file.verilog" enable="1"/>
10+
<File path="C:/Gowin/projects/vector06cc/src/border_delay.v" type="file.verilog" enable="1"/>
11+
<File path="C:/Gowin/projects/vector06cc/src/floppy/dma_rw.v" type="file.verilog" enable="1"/>
12+
<File path="C:/Gowin/projects/vector06cc/src/floppy/floppy.v" type="file.verilog" enable="0"/>
13+
<File path="C:/Gowin/projects/vector06cc/src/floppy/floppy_neo430.v" type="file.verilog" enable="1"/>
14+
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/neo430_cpu.v" type="file.verilog" enable="0"/>
15+
<File path="C:/Gowin/projects/vector06cc/src/floppy/spi.v" type="file.verilog" enable="1"/>
16+
<File path="C:/Gowin/projects/vector06cc/src/floppy/timer100hz.v" type="file.verilog" enable="1"/>
17+
<File path="C:/Gowin/projects/vector06cc/src/floppy/upi_uart/uart.v" type="file.verilog" enable="0"/>
18+
<File path="C:/Gowin/projects/vector06cc/src/floppy/verilog-6502-copy/ALU.v" type="file.verilog" enable="1"/>
19+
<File path="C:/Gowin/projects/vector06cc/src/floppy/verilog-6502-copy/cpu.v" type="file.verilog" enable="1"/>
20+
<File path="C:/Gowin/projects/vector06cc/src/floppy/wd1793.v" type="file.verilog" enable="1"/>
21+
<File path="C:/Gowin/projects/vector06cc/src/i8253/8253.v" type="file.verilog" enable="1"/>
22+
<File path="C:/Gowin/projects/vector06cc/src/keyboard/keymatrix_ram.v" type="file.verilog" enable="1"/>
23+
<File path="C:/Gowin/projects/vector06cc/src/keyboard/ps2k.v" type="file.verilog" enable="1"/>
24+
<File path="C:/Gowin/projects/vector06cc/src/keyboard/scan2matrix.v" type="file.verilog" enable="1"/>
25+
<File path="C:/Gowin/projects/vector06cc/src/keyboard/vectorkeys.v" type="file.verilog" enable="0"/>
26+
<File path="C:/Gowin/projects/vector06cc/src/keyboard/vectorkeys2.v" type="file.verilog" enable="1"/>
27+
<File path="C:/Gowin/projects/vector06cc/src/oneshot.v" type="file.verilog" enable="1"/>
28+
<File path="C:/Gowin/projects/vector06cc/src/osd/chargen.v" type="file.verilog" enable="0"/>
29+
<File path="C:/Gowin/projects/vector06cc/src/osd/screenbuffer.v" type="file.verilog" enable="0"/>
30+
<File path="C:/Gowin/projects/vector06cc/src/osd/textmode.v" type="file.verilog" enable="1"/>
31+
<File path="C:/Gowin/projects/vector06cc/src/ramdisk/kvaz.v" type="file.verilog" enable="1"/>
32+
<File path="C:/Gowin/projects/vector06cc/src/specialkeys.v" type="file.verilog" enable="1"/>
33+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/audio/I2C_AV_Config.v" type="file.verilog" enable="0"/>
34+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/audio/I2C_Controller.v" type="file.verilog" enable="0"/>
35+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/audio/audio_io.v" type="file.verilog" enable="1"/>
36+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/blackvideo/VGAMod.v" type="file.verilog" enable="1"/>
37+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/bootrom/bootrom.v" type="file.verilog" enable="1"/>
38+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/clockster.v" type="file.verilog" enable="1"/>
39+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/gowin_rpll48p24/gowin_rpll48p24.v" type="file.verilog" enable="1"/>
40+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/hidkeyboard/hidmatrix.v" type="file.verilog" enable="1"/>
41+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/hidkeyboard/uarthid.v" type="file.verilog" enable="1"/>
42+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/k580vv55.v" type="file.verilog" enable="1"/>
43+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/multikvaz.v" type="file.verilog" enable="1"/>
44+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/palette_ram/palette_ram.v" type="file.verilog" enable="1"/>
45+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/psram/psram_controller.v" type="file.verilog" enable="1"/>
46+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/ram.v" type="file.verilog" enable="1"/>
47+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/rom.v" type="file.verilog" enable="1"/>
48+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/soundcodec.v" type="file.verilog" enable="1"/>
49+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/uart/haltmode.v" type="file.verilog" enable="1"/>
50+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/uart/intelhex_rx.v" type="file.verilog" enable="1"/>
51+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/uart/uart_rx.v" type="file.verilog" enable="1"/>
52+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/uart/uart_tx.v" type="file.verilog" enable="1"/>
53+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/uart/uart_tx_V2.v" type="file.verilog" enable="1"/>
54+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/vector06cc.v" type="file.verilog" enable="1"/>
55+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/vi53/k580vi53.v" type="file.verilog" enable="1"/>
56+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/video/vga_refresh.v" type="file.verilog" enable="1"/>
57+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/video/video.v" type="file.verilog" enable="1"/>
58+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/video/videomod.v" type="file.verilog" enable="1"/>
59+
<File path="C:/Gowin/projects/vector06cc/src/tangnano9k/vram.v" type="file.verilog" enable="1"/>
60+
<File path="C:/Gowin/projects/vector06cc/src/video/framebuffer.v" type="file.verilog" enable="1"/>
61+
<File path="C:/Gowin/projects/vector06cc/src/video/rambuffer.v" type="file.verilog" enable="1"/>
62+
<File path="C:/Gowin/projects/vector06cc/src/video/shiftreg2.v" type="file.verilog" enable="1"/>
63+
<File path="C:/Gowin/projects/vector06cc/src/vm80/vm80a.v" type="file.verilog" enable="1"/>
64+
<File path="C:/Gowin/projects/vector06cc/src/T80/T80.vhd" type="file.vhdl" enable="1"/>
65+
<File path="C:/Gowin/projects/vector06cc/src/T80/T8080se.vhd" type="file.vhdl" enable="1"/>
66+
<File path="C:/Gowin/projects/vector06cc/src/T80/T80_ALU.vhd" type="file.vhdl" enable="1"/>
67+
<File path="C:/Gowin/projects/vector06cc/src/T80/T80_MCode.vhd" type="file.vhdl" enable="1"/>
68+
<File path="C:/Gowin/projects/vector06cc/src/T80/T80_Pack.vhd" type="file.vhdl" enable="1"/>
69+
<File path="C:/Gowin/projects/vector06cc/src/T80/T80_Reg.vhd" type="file.vhdl" enable="1"/>
70+
<File path="C:/Gowin/projects/vector06cc/src/T80/T80sef.vhd" type="file.vhdl" enable="1"/>
71+
<File path="C:/Gowin/projects/vector06cc/src/ay/ay8910.vhd" type="file.vhdl" enable="1"/>
72+
<File path="C:/Gowin/projects/vector06cc/src/ay/ym2149.vhd" type="file.vhdl" enable="1"/>
73+
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_addr_gen.vhd" type="file.vhdl" enable="1" library="neo430"/>
74+
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_alu.vhd" type="file.vhdl" enable="1" library="neo430"/>
75+
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_control.vhd" type="file.vhdl" enable="1" library="neo430"/>
76+
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_cpu.vhd" type="file.vhdl" enable="1" library="neo430"/>
77+
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_package.vhd" type="file.vhdl" enable="1" library="neo430"/>
78+
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/core/neo430_reg_file.vhd" type="file.vhdl" enable="1" library="neo430"/>
79+
<File path="C:/Gowin/projects/vector06cc/src/floppy/neo430/neo430_cpu_std_logic.vhd" type="file.vhdl" enable="1"/>
80+
<File path="C:/Gowin/projects/vector06cc/src/floppy/uart/txd.vhd" type="file.vhdl" enable="1"/>
81+
<File path="C:/Gowin/projects/vector06cc/src/i82c55/i82c55.vhd" type="file.vhdl" enable="1"/>
8282
<File path="src/tangnano9k.cst" type="file.cst" enable="1"/>
8383
<File path="src/vector06cc.sdc" type="file.sdc" enable="1"/>
8484
<File path="src/clocks.rao" type="file.gao" enable="0"/>

‎src/tangnano9k/config.v‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,6 +18,7 @@
1818

1919
`define WITH_FLOPPY
2020
`define WITH_OSD
21+
2122
//`define WITH_SDRAM
2223
`define WITH_PSRAM // Tang Nano 9K GW1N-NR9 Q88P
2324
//`define FLOPPYLESS_HAX // set FDC odata to $00 when compiling without floppy

‎src/tangnano9k/video/vga_refresh.v‎

Lines changed: 22 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -33,10 +33,14 @@ module vga_refresh(
3333
output lcd_den_o,
3434
output lcd_hsync_o,
3535
output lcd_vsync_o,
36-
output [9:0] lcd_y,
37-
output lcd_newline_o, // single clock hs
36+
output [9:0] lcd_x_o,
37+
output [9:0] lcd_y_o,
3838
output hsync,
3939
output vsync,
40+
output lcd_newline_o, // single clock lcd hsync (+)
41+
output vga_newline_o, // single clock vga hsync (+)
42+
output tv_newline_o, // single clock tv hsync (+)
43+
output loadscroll_o,
4044
output YPbPrvsync,
4145
output videoActive,
4246
output bordery,
@@ -98,6 +102,11 @@ assign lcd_clk_o = clk24;
98102

99103
parameter state0 = 3'b000, state1 = 3'b001, state2 = 3'b010, state3 = 3'b011, state4 = 3'b100, state5 = 3'b101, state6 = 3'b110, state7 = 3'b111;
100104

105+
reg [7:0] testreg = 0;
106+
reg [6:0] testreg2 = 0;
107+
108+
assign loadscroll_o = scanyy_state == state5 && realx == SCROLLLOAD_X && scanyy == VISIBLEHEIGHT;
109+
101110
always @(posedge clk24) begin
102111
if (scanyy == 0) begin
103112
case (scanyy_state)
@@ -203,7 +212,7 @@ always @(posedge clk24) begin
203212
scanxx <= scanxx - 1'b1;
204213

205214
// load scroll register at this precise moment
206-
if (scanyy_state == state5 && realx == SCROLLLOAD_X && scanyy == VISIBLEHEIGHT) begin
215+
if (loadscroll_o) begin
207216
fb_row <= {video_scroll_reg, 1'b1};
208217
fb_row_count <= 511;
209218
end
@@ -246,6 +255,14 @@ reg [9:0] lcd_visible_time = 0;
246255
reg lcd_newline = 0;
247256
assign lcd_newline_o = lcd_newline;
248257

258+
reg vga_hsync_r = 0;
259+
always @(posedge clk24) vga_hsync_r <= hsync;
260+
assign vga_newline_o = vga_hsync_r && ~hsync;
261+
262+
reg tv_hsync_r = 0;
263+
always @(posedge clk24) tv_hsync_r <= tvhs;
264+
assign tv_newline_o = tv_hsync_r && ~tvhs;
265+
249266
always @(posedge clk24)
250267
begin
251268
vsync_r <= vsync;
@@ -288,23 +305,11 @@ begin
288305

289306
end
290307

291-
292-
// example:
293-
// DE = time >= 63 && time <= 856
294-
// HS = >=11 <11+56
295-
296-
297308
reg lcd_hsync_r = 0;
298309
always @(posedge clk24)
299310
lcd_hsync_r <= ~(lcd_time >= 11 && lcd_time < (11+56)) | ~vsync;
300-
//lcd_hsync_r <= ~(lcd_time >= 15 && lcd_time < (11+56)) | ~vsync;
301311

302312
reg lcd_den_r = 0;
303-
//always @(posedge clk24)
304-
// lcd_den_r = lcd_time >= 76
305-
// && (lcd_time < lcd_visible_time - 55)
306-
// && (sim_lcd_line >= 23) && (sim_lcd_line < 503);
307-
308313
always @(posedge clk24)
309314
lcd_den_r = lcd_time >= (11 + 56)
310315
&& (lcd_time < lcd_visible_time - 9) // 9 shows boot on both, 7 stops working on 7"
@@ -318,7 +323,8 @@ assign lcd_den_o = lcd_den_r;
318323
assign lcd_den_o = videoActiveY && lcd_active_x;
319324
`endif
320325

321-
assign lcd_y = sim_lcd_line - 23;
326+
assign lcd_y_o = sim_lcd_line - 23;
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assign lcd_x_o = lcd_time;
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endmodule
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