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Users following verilator

@Saga4
Sarthak Agarwal Saga4
Experiencing sweet pain of building

Building Codeflash.ai

@RSREDDY2ec
RSREDDY2ec
VLSI Design Verification Engineer | SystemVerilog | UVM
@Dharshan-John
Dharshan J Dharshan-John
Currently pursuing B.E ECE in SSN and passionate about solving problems in the aspect of engineering and especially using electronics.
@Kathakutty
kathakutty Kathakutty
I'm an ece student and I'm also an aspirant to a vlsi engineer .
@enumouse
enumouse enumouse
bleh. interests in WASM, compilers, networking, and kernels. I love RISC-V and Arm.

United Kingdom

@eidotal
Eido Tal eidotal
Design Verification Architect & Technical Lead SystemVerilog/UVM | SoC / Smart-NIC
@CHIRRANJEAVI
Chirranjeavi Moorthi CHIRRANJEAVI
Robotics, ML & VLSI engineer building future chips for autonomous cars & intelligent robots | Computer architecture & AI hardware

NYC, New York

@tusharpathaknyu
Tushar Pathak tusharpathaknyu

New York University New York

@AntonioBerna
Antonio Bernardini AntonioBerna
Computer Engineering Student passionate about cybersecurity, hardware, firmware, and software, sharing knowledge through innovative projects and impactful code.

@intornoapp Rome

@AIAccelSid
AIAccelSid
Unlocking the Potential of Machine Learning and Hardware Acceleration
@29Sam
Supriya A. Mishra 29Sam
Second year EE student at IIT Bombay, Interested in Problem Solving

EE B.tech, IIT Bombay Mumbai, India

@SanjayRich
Sanjay Karthikeyan SanjayRich
Electronics and Communication Engineering Undergrad @ VIT Vellore | VLSI

Vit Vellore Chennai,Tamil Nadu

@sjanaX01
Subhadip Jana sjanaX01
Focuse only

Kolkata, West Bengal

@TejashwiVulupala
Vulupala tejashwi reddy TejashwiVulupala
Embedded Systems & VLSI engineer | RTL & SystemVerilog | RISC-V SoC design on Zynq UltraScale+ | Passionate about verification, hardware/software co-design, and

Chaitanya bharathi institute of technology hyderabad

@MadhanSaiKrishna
Madhan Sai Krishna MadhanSaiKrishna
Design & Build

IIIT Hyderabad Gachibowli, Hyderabad, Telangana

@raulbehl
raulbehl
Computer Architecture Enthusiast, Verilog & Assembly level programmer
@CarloPalanca
Carlo Palanca CarloPalanca
Electronics Engineer & Technician

Meycauayan, Bulacan

@pierav
PIRX pierav
Microarchitect

Grenoble

@Biancaa-R
Biancaa Ramesh Biancaa-R
ECE undergrad @ SSN '26