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quest 25: Refactor comments for consistency and clarity in tb_flip_flop_array
1 parent 1501b28 commit eb74f9a

1 file changed

Lines changed: 11 additions & 11 deletions

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ip/25_Flip_Flop_Array/tb_flip_flop_array.vhd

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -47,9 +47,9 @@ architecture tb of tb_flip_flop_array is
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begin
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generate_clock(clk => clk, FREQ => real(1 sec / CLK_PERIOD));
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50-
------------------------------------------------------------
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------------------------------------------------------------
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-- VUnit
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------------------------------------------------------------
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------------------------------------------------------------
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test_runner_watchdog(runner, SIM_TIMEOUT);
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main: process
@@ -66,7 +66,7 @@ begin
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test_runner_cleanup(runner);
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wait;
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end process;
69-
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checker: process
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constant PROPAGATION_TIME: time := 1 ns;
@@ -197,13 +197,13 @@ begin
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11 => 0, -- Write again to address 0
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12 => 1, -- Read from address 1 (shouldn't change)
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13 => 0, -- Read from address 0 (should be changed)
200-
14 => 7, --
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15 => 7, --
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16 => 255, --
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17 => 255, --
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18 => 10, --
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19 => 10, --
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20 => 0 --
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14 => 7, --
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15 => 7, --
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16 => 255, --
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17 => 255, --
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18 => 10, --
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19 => 10, --
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20 => 0 --
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);
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constant DIN_SEQUENCE: integer_vector := (
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0 => 16#00#, -- Reset
@@ -258,7 +258,7 @@ begin
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begin
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info("2.0) test_all_combinations");
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-- Initialize expected output array
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-- Initialise expected output array
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expected_dout_array := new_1d(length => 2**ADDRESS_WIDTH, bit_width => DATA_WIDTH, is_signed => false);
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for i in ADDR_SEQUENCE'low to ADDR_SEQUENCE'high loop

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