@@ -47,9 +47,9 @@ architecture tb of tb_flip_flop_array is
4747begin
4848 generate_clock(clk => clk, FREQ => real (1 sec / CLK_PERIOD));
4949
50- ------------------------------------------------------------
50+ ------------------------------------------------------------
5151 -- VUnit
52- ------------------------------------------------------------
52+ ------------------------------------------------------------
5353 test_runner_watchdog(runner, SIM_TIMEOUT);
5454
5555 main: process
6666 test_runner_cleanup(runner);
6767 wait ;
6868 end process ;
69-
69+
7070
7171 checker: process
7272 constant PROPAGATION_TIME: time := 1 ns ;
@@ -197,13 +197,13 @@ begin
197197 11 => 0 , -- Write again to address 0
198198 12 => 1 , -- Read from address 1 (shouldn't change)
199199 13 => 0 , -- Read from address 0 (should be changed)
200- 14 => 7 , --
201- 15 => 7 , --
202- 16 => 255 , --
203- 17 => 255 , --
204- 18 => 10 , --
205- 19 => 10 , --
206- 20 => 0 --
200+ 14 => 7 , --
201+ 15 => 7 , --
202+ 16 => 255 , --
203+ 17 => 255 , --
204+ 18 => 10 , --
205+ 19 => 10 , --
206+ 20 => 0 --
207207 );
208208 constant DIN_SEQUENCE: integer_vector := (
209209 0 => 16#00# , -- Reset
@@ -258,7 +258,7 @@ begin
258258 begin
259259 info(" 2.0) test_all_combinations" );
260260
261- -- Initialize expected output array
261+ -- Initialise expected output array
262262 expected_dout_array := new_1d(length => 2 ** ADDRESS_WIDTH, bit_width => DATA_WIDTH, is_signed => false );
263263
264264 for i in ADDR_SEQUENCE'low to ADDR_SEQUENCE'high loop
0 commit comments