Fix: Add bullet points to Input and Output Signals sections in all READMEs

Author: nselvara

ip/01_Simple_Router/README.md

@@ -12,21 +12,25 @@ The input has an enable signal (din_en), which allows the input to be forwarded
 
 ### Input and Output Signals
 
-`din` - Input data
-`din_en` - Enable signal for din. Forwards data from input to an output if 1, does not forward data otherwise
-`addr` - Two bit destination address. For example addr = b11 = 3 indicates din should be forwarded to output value 3 (dout3)
-`dout0` - Output 0. Corresponds to addr = b00
-`dout1` - Output 1. Corresponds to addr = b01
-`dout2` - Output 2. Corresponds to addr = b10
-`dout3` - Output 3. Corresponds to addr = b11
+- `din` - Input data
+- `din_en` - Enable signal for din. Forwards data from input to an output if 1, does not forward data otherwise
+- `addr` - Two bit destination address. For example addr = b11 = 3 indicates din should be forwarded to output value 3 (dout3)
+- `dout0` - Output 0. Corresponds to addr = b00
+- `dout1` - Output 1. Corresponds to addr = b01
+- `dout2` - Output 2. Corresponds to addr = b10
+- `dout3` - Output 3. Corresponds to addr = b11
 
 > [!NOTE]
 > For the complete problem description, please visit:
 > <https://chipdev.io/question/1>
 
 ## Description
 
-Combinational router using a `case` statement to decode the 2-bit address and route input data to one of four outputs. All outputs default to zero, then the selected output is conditionally assigned when `din_en` is high. Synthesises to a simple 4:1 demultiplexer with AND gates gating the enable signal.
+Combinational router using a `case` statement to decode the 2-bit address and route input data to one of four outputs.
+All outputs default to zero, then the selected output is conditionally assigned when `din_en` is high.
+Synthesises to a simple 4:1 demultiplexer with AND gates gating the enable signal.
+
+---
 
 ## Source
 

ip/02_Second_Largest/README.md

@@ -10,14 +10,14 @@ When the reset-low signal (`resetn`) goes low, all previous values seen in the i
 
 ### Input and Output Signals
 
-`clk` - Clock signal
-`resetn` - Synchronous reset-low signal
-`din` - Input data sequence
-`dout` - Second-largest value seen so far
+- `clk` - Clock signal
+- `resetn` - Synchronous reset-low signal
+- `din` - Input data sequence
+- `dout` - Second-largest value seen so far
 
 ### Output signals during reset
 
-`dout` - 0 when resetn is active
+- `dout` - 0 when resetn is active
 
 > [!NOTE]
 > For the complete problem description, please visit:

ip/03_Rounding_Division/README.md

@@ -8,8 +8,8 @@ Divide an input number by a power of two and round the result to the nearest int
 
 ### Input and Output Signals
 
-`din` - Input number
-`dout` - Rounded result
+- `din` - Input number
+- `dout` - Rounded result
 
 > [!NOTE]
 > For the complete problem description, please visit:
@@ -22,6 +22,8 @@ The division is accomplished via right-shift by `DIV_LOG2` positions.
 The rounding logic examines the bit at position `DIV_LOG2-1` (representing the 0.5 threshold) - if this bit is set, it adds 1 to the quotient.
 The `resize()` function handles saturation when the result overflows the output width.
 
+---
+
 ## Source
 
 This quest is from [chipdev.io](https://chipdev.io/question/3).

ip/04_Bit_Reverser/README.md

@@ -19,13 +19,13 @@ When the reset-low signal (resetn) goes to 0, the Gray code sequence should rest
 
 ### Input and Output Signals
 
-`clk` - Clock signal
-`resetn` - Synchronous reset-low signal
-`out` - Gray code counter value
+- `clk` - Clock signal
+- `resetn` - Synchronous reset-low signal
+- `out` - Gray code counter value
 
 ### Output signals during reset
 
-`out` - 0 when resetn is active
+- `out` - 0 when resetn is active
 
 > [!NOTE]
 > For the complete problem description, please visit:
@@ -36,6 +36,8 @@ When the reset-low signal (resetn) goes to 0, the Gray code sequence should rest
 Combinational bit-reversal circuit using a loop that maps `dout(i) <= din(din'high - i)` to mirror the input vector.
 Synthesises to pure wiring with no logic gates required.
 
+---
+
 ## Source
 
 This quest is from [chipdev.io](https://chipdev.io/question/4).

ip/05_Gray_Code_Converter/README.md

@@ -8,8 +8,8 @@ Reverse the bits of an input value's binary representation.
 
 ### Input and Output Signals
 
-`din` - Input value
-`dout` - Bitwise reversed value
+- `din` - Input value
+- `dout` - Bitwise reversed value
 
 > [!NOTE]
 > For the complete problem description, please visit:
@@ -21,6 +21,8 @@ Sequential Gray code counter implemented as a binary counter with conversion out
 Each clock cycle increments a binary counter variable, then converts it to Gray code using the standard formula: `gray = count XOR shift_right(count, 1)`.
 This produces the characteristic Gray code property where consecutive values differ by only one bit.
 
+---
+
 ## Source
 
 This quest is from [chipdev.io](https://chipdev.io/question/5).

ip/06_Edge_Detector/README.md

@@ -10,14 +10,14 @@ Bonus - can you enhance your design to pulse `dout` on the same cycle as the ris
 
 ### Input and Output Signals
 
-`clk` - Clock signal
-`resetn` - Synchronous reset-low signal
-`din` - Input signal
-`dout` - Output signal
+- `clk` - Clock signal
+- `resetn` - Synchronous reset-low signal
+- `din` - Input signal
+- `dout` - Output signal
 
 ### Output signals during reset
 
-`dout` - `0` when `resetn` is active
+- `dout` - `0` when `resetn` is active
 
 > [!NOTE]
 > For the complete problem description, please visit:
@@ -28,6 +28,8 @@ Bonus - can you enhance your design to pulse `dout` on the same cycle as the ris
 Rising edge detector that registers the previous input value each clock cycle and outputs a single-cycle pulse when `din='1'` and differs from the registered value.
 The comparison `din /= din_reg` detects the transition, while the `din = '1'` check ensures it's specifically a rising edge.
 
+---
+
 ## Source
 
 This quest is from [chipdev.io](https://chipdev.io/question/6).

ip/07_Serialiser/README.md

@@ -14,15 +14,15 @@ When reset (`resetn`) is active, the input value that is being shifted is treate
 
 ### Input and Output Signals
 
-`clk` - Clock signal
-`resetn` - Synchronous reset-low signal
-`din` - Input signal
-`din_en` - Enable signal for input data
-`dout` - Output signal
+- `clk` - Clock signal
+- `resetn` - Synchronous reset-low signal
+- `din` - Input signal
+- `din_en` - Enable signal for input data
+- `dout` - Output signal
 
 ### Output signals during reset
 
-`dout` - `0` when `resetn` is active
+- `dout` - `0` when `resetn` is active
 
 > [!NOTE]
 > For the complete problem description, please visit:
@@ -39,6 +39,8 @@ Serializer that captures a parallel input word when `din_en` asserts and shifts
 A `bit_index` counter tracks which bit to output, incrementing from 0 to `DATA_WIDTH-1`.
 The captured data remains in `din_reg` until the entire word is transmitted, then zeros out.
 
+---
+
 ## Source
 
 This quest is from [chipdev.io](https://chipdev.io/question/7).

ip/08_Deserialiser/README.md

@@ -10,14 +10,14 @@ Once the number of input bits received is larger than `DATA_WIDTH`, only the `DA
 
 ### Input and Output Signals
 
-`clk` - Clock signal
-`resetn` - Synchronous reset-low signal
-`din` - Input signal
-`dout` - Output signal
+- `clk` - Clock signal
+- `resetn` - Synchronous reset-low signal
+- `din` - Input signal
+- `dout` - Output signal
 
 ### Output signals during reset
 
-`dout` - `0` when `resetn` is active
+- `dout` - `0` when `resetn` is active
 
 > [!NOTE]
 > For the complete problem description, please visit:
@@ -34,6 +34,8 @@ Deserialiser that reconstructs a parallel word from serial input.
 Each clock cycle shifts the output register left and inserts the new `din` bit at the LSB position using the concatenation `dout <= dout(dout'high - 1 downto 0) & din`.
 After `DATA_WIDTH` clock cycles, the complete word appears at the output.
 
+---
+
 ## Source
 
 This quest is from [chipdev.io](https://chipdev.io/question/8).

ip/09_Fibonacci_Generator/README.md

@@ -18,13 +18,13 @@ The sequence should be produced when the active low signal (`resetn`) becomes ac
 
 ### Input and Output Signals
 
-`clk` - Clock signal
-`resetn` - Synchronous reset-low signal
-`out` - Current Fibonacci number
+- `clk` - Clock signal
+- `resetn` - Synchronous reset-low signal
+- `out` - Current Fibonacci number
 
 ### Output signals during reset
 
-`out` - `1` when `resetn` is active (the first `1` of the Fibonacci sequence)
+- `out` - `1` when `resetn` is active (the first `1` of the Fibonacci sequence)
 
 > [!NOTE]
 > For the complete problem description, please visit:
@@ -41,6 +41,8 @@ Fibonacci sequence generator using a 2-element pipeline holding the previous two
 Each clock cycle computes `sum = fib[1] + fib[0]`, then shifts the pipeline left, discarding the oldest value and inserting the new sum.
 The pipeline initialises to `[1, 1]` and produces the sequence 1, 1, 2, 3, 5, 8, 13...
 
+---
+
 ## Source
 
 This quest is from [chipdev.io](https://chipdev.io/question/9).

ip/10_Counting_Ones/README.md

@@ -8,8 +8,8 @@ Given an input binary value, output the number of bits that are equal to `1`.
 
 ### Input and Output Signals
 
-`din` - Input value
-`dout` - Number of `1`'s in the input value
+- `din` - Input value
+- `dout` - Number of `1`'s in the input value
 
 > [!NOTE]
 > For the complete problem description, please visit:
@@ -21,6 +21,8 @@ Population count (popcount) circuit that returns the number of '1' bits in the i
 Implemented using the `get_amount_of_state()` utility function from the utils package which counts occurrences of a specified bit state.
 The output width is `ceil(log2(DATA_WIDTH))` bits to accommodate the maximum possible count.
 
+---
+
 ## Source
 
 This quest is from [chipdev.io](https://chipdev.io/question/10).