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quest 34: Added HDL, tb & wave for mealy_finite_state_machine 
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‎ip/34_Mealy_Finite_State_Machine/mealy_finite_state_machine.vhd‎

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--! ----------------------------------------------------------------------------
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--! @author N. Selvarajah
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--! @brief Based on chipdev.io question 34
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--! @details VHDL module for Mealy Finite State Machine
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--! @details Ouputs depend on both the present state and the current inputs.
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--! ----------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity mealy_finite_state_machine is
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port (
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clk: in std_ulogic;
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rst_n: in std_ulogic;
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din: in std_ulogic;
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cen: in std_ulogic;
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doutx: out std_ulogic;
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douty: out std_ulogic
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);
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end entity;
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architecture behavioural of mealy_finite_state_machine is
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type state_t is (S0, S1, S2, S3, S4);
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signal present_state, next_state: state_t;
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signal din_reg: std_ulogic;
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signal cen_reg: std_ulogic;
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begin
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state_register: process(clk, rst_n)
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begin
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if rst_n = '0' then
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present_state <= S0;
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din_reg <= '0';
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cen_reg <= '0';
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elsif rising_edge(clk) then
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present_state <= next_state;
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din_reg <= din;
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cen_reg <= cen;
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end if;
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end process;
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next_state_logic: process(present_state, din_reg)
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begin
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next_state <= present_state;
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case present_state is
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-- Initial state
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when S0 =>
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next_state <= S3 when din_reg else S1;
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-- Saw one 0 or two or more 0s (000, 010, 100, 110)
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when S1 | S2 =>
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next_state <= S3 when din_reg else S2;
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-- Saw one 1 or two or more 1s (111, 101, 011, 001)
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when S3 | S4 =>
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next_state <= S4 when din_reg else S1;
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when others =>
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next_state <= S0;
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end case;
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end process;
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output_logic: process(present_state, din_reg, cen_reg)
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begin
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doutx <= '0';
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douty <= '0';
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if ((present_state = S1 or present_state = S2) and din_reg = '0') or ((present_state = S3 or present_state = S4) and din_reg = '1') then
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doutx <= cen_reg;
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end if;
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if (present_state = S2 and din_reg = '0') or (present_state = S4 and din_reg = '1') then
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douty <= cen_reg;
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end if;
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end process;
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end architecture;

‎ip/34_Mealy_Finite_State_Machine/tb_mealy_finite_state_machine.do‎

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onerror {resume}
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quietly WaveActivateNextPane {} 0
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add wave -noupdate -divider DuT
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add wave -noupdate -divider Interface
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add wave -noupdate /tb_mealy_finite_state_machine/clk
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add wave -noupdate /tb_mealy_finite_state_machine/rst_n
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add wave -noupdate /tb_mealy_finite_state_machine/din
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add wave -noupdate /tb_mealy_finite_state_machine/cen
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add wave -noupdate /tb_mealy_finite_state_machine/doutx
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add wave -noupdate /tb_mealy_finite_state_machine/douty
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add wave -noupdate -divider Internal
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add wave -noupdate /tb_mealy_finite_state_machine/DuT/present_state
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add wave -noupdate /tb_mealy_finite_state_machine/DuT/next_state
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add wave -noupdate /tb_mealy_finite_state_machine/DuT/din_reg
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add wave -noupdate /tb_mealy_finite_state_machine/DuT/cen_reg
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add wave -noupdate -divider {tb - Internal}
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add wave -noupdate /tb_mealy_finite_state_machine/simulation_done
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TreeUpdate [SetDefaultTree]
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WaveRestoreCursors {{Cursor 1} {1975000 ps} 0}
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quietly wave cursor active 1
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configure wave -namecolwidth 150
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configure wave -valuecolwidth 100
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configure wave -justifyvalue left
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configure wave -signalnamewidth 1
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configure wave -snapdistance 10
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configure wave -datasetprefix 0
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configure wave -rowmargin 4
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configure wave -childrowmargin 2
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configure wave -gridoffset 0
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configure wave -gridperiod 1
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configure wave -griddelta 40
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configure wave -timeline 0
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configure wave -timelineunits ns
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update
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WaveRestoreZoom {0 ps} {10889550 ps}

‎ip/34_Mealy_Finite_State_Machine/tb_mealy_finite_state_machine.vhd‎

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--! ----------------------------------------------------------------------------
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--! @author N. Selvarajah
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--! @brief Based on chipdev.io question 34
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--! @details VHDL module for Mealy Finite State Machine
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--! ----------------------------------------------------------------------------
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-- vunit: run_all_in_same_sim
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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library vunit_lib;
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context vunit_lib.vunit_context;
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library osvvm;
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use osvvm.RandomPkg.RandomPType;
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use osvvm.RandomPkg.NaturalVSlType;
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use osvvm.CoveragePkg.all;
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use work.tb_utils.all;
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entity tb_mealy_finite_state_machine is
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generic (
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runner_cfg: string := runner_cfg_default
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);
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end entity;
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architecture tb of tb_mealy_finite_state_machine is
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constant SIM_TIMEOUT: time := 1 ms;
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constant CLK_PERIOD: time := 10 ns;
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constant ENABLE_DEBUG_PRINT: boolean := false;
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signal clk: std_ulogic := '0';
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signal rst_n: std_ulogic := '0';
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signal din: std_ulogic := '0';
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signal cen: std_ulogic := '0';
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signal doutx: std_ulogic;
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signal douty: std_ulogic;
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signal simulation_done: boolean := false;
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begin
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generate_clock(clk => clk, FREQ => real(1 sec / CLK_PERIOD));
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------------------------------------------------------------
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-- VUnit
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------------------------------------------------------------
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test_runner_watchdog(runner, SIM_TIMEOUT);
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main: process
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begin
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test_runner_setup(runner, runner_cfg);
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info("Starting tb_mealy_finite_state_machine");
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if ENABLE_DEBUG_PRINT then
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show(display_handler, debug);
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end if;
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wait until simulation_done;
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log("Simulation done, all tests passed!");
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test_runner_cleanup(runner);
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wait;
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end process;
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checker: process
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constant PROPAGATION_TIME: time := 1 ns;
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variable random: RandomPType;
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variable coverage_model: CovPType;
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procedure wait_clk_cycles(n: positive) is begin
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for i in 1 to n loop
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wait until rising_edge(clk);
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end loop;
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wait for PROPAGATION_TIME;
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end procedure;
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procedure reset_module is begin
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rst_n <= '0';
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wait_clk_cycles(1);
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end procedure;
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procedure start_module is begin
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rst_n <= '1';
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end procedure;
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procedure test_example_1 is
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constant RST_N_SEQUENCE: std_ulogic_vector := (
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0 => '0', 1 to 7 => '1', 8 => '0', 9 to 13 => '1'
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);
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constant DIN_SEQUENCE: RST_N_SEQUENCE'subtype := (
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0 to 1 => '0', 2 to 8 => '1', 9 => '0', 10 => '1', others => '0'
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);
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constant CEN_SEQUENCE: RST_N_SEQUENCE'subtype := (
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9 | 12 to 13 => '0', others => '1'
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);
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constant EXPECTED_DOUTX_SEQUENCE: RST_N_SEQUENCE'subtype := "01011111000000";
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constant EXPECTED_DOUTY_SEQUENCE: RST_N_SEQUENCE'subtype := "00001111000000";
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begin
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info("1.0) test_example_1" & LF);
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for i in RST_N_SEQUENCE'range loop
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rst_n <= RST_N_SEQUENCE(i);
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din <= DIN_SEQUENCE(i);
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cen <= CEN_SEQUENCE(i);
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wait_clk_cycles(1);
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check_equal(got => doutx, expected => EXPECTED_DOUTX_SEQUENCE(i), msg => "doutx at cycle " & to_string(i));
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check_equal(got => douty, expected => EXPECTED_DOUTY_SEQUENCE(i), msg => "douty at cycle " & to_string(i));
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end loop;
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info("test_example_1 passed!" & LF);
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end procedure;
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procedure test_zeros is
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constant REPETITIONS: positive := 10;
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begin
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info("2.0) test_zeros" & LF);
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reset_module;
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start_module;
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cen <= '1';
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din <= '0';
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-- After reset, din_reg='0' already counts as first value
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-- So: i=1 -> 2 consecutive 0s (doutx='1'), i=2 -> 3 consecutive 0s (douty='1')
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for i in 1 to REPETITIONS loop
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wait_clk_cycles(1);
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check_equal(got => doutx, expected => '1', msg => "doutx at cycle " & to_string(i));
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check_equal(got => douty, expected => (i >= 2), msg => "douty at cycle " & to_string(i));
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end loop;
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info("test_zeros passed!" & LF);
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end procedure;
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procedure test_ones is
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constant REPETITIONS: positive := 10;
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begin
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info("3.0) test_ones" & LF);
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reset_module;
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start_module;
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cen <= '1';
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din <= '1';
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for i in 1 to REPETITIONS loop
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wait_clk_cycles(1);
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check_equal(got => doutx, expected => (i >= 2), msg => "doutx at cycle " & to_string(i));
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check_equal(got => douty, expected => (i >= 3), msg => "douty at cycle " & to_string(i));
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end loop;
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info("test_ones passed!" & LF);
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end procedure;
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procedure test_random is
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constant CEN_WEIGHT: NaturalVSlType(std_ulogic'('0') to '1') := ('0' => 20, '1' => 80);
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constant TOTAL_ITERATIONS: positive := 1000;
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variable din_history: std_ulogic_vector(2 downto 0) := (others => '0');
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variable history_count: natural := 0;
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variable expected_doutx, expected_douty: std_ulogic;
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begin
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info("4.0) test_random" & LF);
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coverage_model.SetName("Random Test Coverage Model");
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coverage_model.AddBins(Name => "rst_n", CovBin => GenBin(Min => 0, Max => 1, NumBin => 1));
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coverage_model.AddBins(Name => "cen", CovBin => GenBin(Min => 0, Max => 1, NumBin => 1));
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coverage_model.AddBins(Name => "din", CovBin => GenBin(Min => 0, Max => 1, NumBin => 1));
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coverage_model.AddBins(Name => "doutx", CovBin => GenBin(Min => 0, Max => 1, NumBin => 1));
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coverage_model.AddBins(Name => "douty", CovBin => GenBin(Min => 0, Max => 1, NumBin => 1));
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rst_n <= '0';
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cen <= '0';
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din <= '0';
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din_history := (others => '0');
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history_count := 0;
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wait_clk_cycles(1);
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for iteration in 1 to TOTAL_ITERATIONS loop
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rst_n <= random.DistSl(weight => RESET_N_WEIGHT);
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cen <= random.DistSl(weight => CEN_WEIGHT);
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din <= to_01(random.RandSl);
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wait_clk_cycles(1);
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-- Update coverage
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coverage_model.ICover(CovPoint => to_integer(unsigned'('0' & rst_n)));
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coverage_model.ICover(CovPoint => to_integer(unsigned'('0' & cen)));
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coverage_model.ICover(CovPoint => to_integer(unsigned'('0' & din)));
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expected_doutx := '0';
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expected_douty := '0';
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if rst_n = '0' then
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din_history := (others => '0');
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history_count := 0;
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else
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din_history := din_history(din_history'high - 1 downto din_history'low) & din;
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history_count := history_count + 1;
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-- Check for 2 consecutive same values (doutx): reset value (din_reg='0') counts as first
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-- So history_count=1 means we have 2 values (reset + current)
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if history_count >= 1 then
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if din_history(1 downto 0) = "00" or din_history(1 downto 0) = "11" then
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expected_doutx := cen;
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end if;
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end if;
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-- Check for 3 consecutive same values (douty): reset value counts as first
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-- So history_count=2 means we have 3 values (reset + 2 new inputs)
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if history_count >= 2 then
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if din_history = "000" or din_history = "111" then
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expected_douty := cen;
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end if;
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end if;
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end if;
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coverage_model.ICover(CovPoint => to_integer(unsigned'('0' & doutx)));
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coverage_model.ICover(CovPoint => to_integer(unsigned'('0' & douty)));
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check_equal(got => doutx, expected => expected_doutx, msg => "doutx at iteration " & to_string(iteration));
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check_equal(got => douty, expected => expected_douty, msg => "douty at iteration " & to_string(iteration));
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end loop;
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info(
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"Coverage percentage: " & to_string(coverage_model.GetCov, "%.2f") & " %" &
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" (bins covered: " & to_string(coverage_model.GetTotalCovCount) & "/" & to_string(coverage_model.GetNumBins) & ")" & LF
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);
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info("Coverage details:" & LF);
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coverage_model.WriteBin;
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info("test_random passed (" & to_string(TOTAL_ITERATIONS) & " iterations) !" & LF);
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end procedure;
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begin
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random.InitSeed(random'instance_name);
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-- NOTE: Don't remove this, or else VUnit won't be able to run the tests
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wait_clk_cycles(1);
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while test_suite loop
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if run("test_example_1") then
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test_example_1;
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elsif run("test_zeros") then
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test_zeros;
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elsif run("test_ones") then
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test_ones;
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elsif run("test_random") then
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test_random;
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else
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assert false report "No test has been run!" severity failure;
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end if;
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end loop;
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simulation_done <= true;
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wait;
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end process;
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DuT: entity work.mealy_finite_state_machine
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port map (
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clk => clk,
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rst_n => rst_n,
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din => din,
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cen => cen,
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doutx => doutx,
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douty => douty
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);
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end architecture;

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