Skip to content

Commit 3c0364a

Browse files
committed
Added missing type hints.
1 parent 8cd65c5 commit 3c0364a

1 file changed

Lines changed: 4 additions & 4 deletions

File tree

pySVModel/__init__.py

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -52,7 +52,7 @@
5252
__email__ = "Paebbels@gmail.com"
5353
__copyright__ = "2021-2026, Patrick Lehmann"
5454
__license__ = "Apache License, Version 2.0"
55-
__version__ = "0.5.5"
55+
__version__ = "0.5.6"
5656

5757

5858
@export
@@ -114,7 +114,7 @@ class SystemVerilogVersion(Enum):
114114
"Latest": Latest
115115
} #: Dictionary of (System)Verilog year codes variants as integer and strings for mapping to unique enum values.
116116

117-
def __init__(self, *_):
117+
def __init__(self, *_) -> None:
118118
"""Patch the embedded MAP dictionary"""
119119
for k, v in self.__class__.__VERSION_MAPPINGS__.items():
120120
if (not isinstance(v, self.__class__)) and (v == self.value):
@@ -237,7 +237,7 @@ def __str__(self) -> str:
237237
"""
238238
Formats the SystemVerilog version to pattern ``SV'xx`` or in case of classic Verilog to ``Verilog'xx``.
239239
240-
:return: Formatted (System)Verilog version.
240+
:returns: Formatted (System)Verilog version.
241241
"""
242242
if self.value == self.Any.value:
243243
return "SV'Any"
@@ -254,7 +254,7 @@ def __repr__(self) -> str:
254254
"""
255255
Formats the (System)Verilog version to pattern ``xxxx``.
256256
257-
:return: Formatted (System)Verilog version.
257+
:returns: Formatted (System)Verilog version.
258258
"""
259259
if self.value == self.Any.value:
260260
return "Any"

0 commit comments

Comments
 (0)