As an example the instruction csrw mstatus, ra is correctly decoded, but the system register representations are not in include/capstone/riscv.h. This makes it impossible to identify the system register in user code.
I poked around in the importer, but could quite figure out what was missing to make this happen. My guess is that GET_ENUM_VALUES_SysReg from RISCVGenCSSystemOperandsEnum.inc needs to be defined.
$ ./cstool -dar riscv64 73900030
0 73 90 00 30 csrw mstatus, ra
ID: 189 (csrrw)
Is alias: 0 (invalid) with REAL operand set
op_count: 3
operands[0].type: REG = zero
operands[0].access: WRITE
operands[1].type: CSR = mstatus
operands[1].access: READ | WRITE
operands[2].type: REG = ra
operands[2].access: READ
| Questions |
Answers |
| System Capstone runs on OS/arch/bits |
Ubuntu x86_64 |
| Capstone module affected |
riscv |
| Source of Capstone |
git clone |
| Version/git commit |
4ab9943 |
As an example the instruction
csrw mstatus, rais correctly decoded, but the system register representations are not ininclude/capstone/riscv.h. This makes it impossible to identify the system register in user code.I poked around in the importer, but could quite figure out what was missing to make this happen. My guess is that
GET_ENUM_VALUES_SysRegfrom RISCVGenCSSystemOperandsEnum.inc needs to be defined.git clone