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Enabled VHDL-2019 for GHDL >= 6.0.0.
Note that VUnit log location support based on call_path is deactivated as this is yet to be supported by GHDL.
1 parent ae8ba6e commit d289f07

4 files changed

Lines changed: 60 additions & 21 deletions

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docs/news.d/1177.feature.rst

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,3 @@
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Enabled VHDL-2019 for GHDL >= 6.0.0.
2+
3+
Note that VUnit log location support based on call_path is deactivated as this is yet to be supported by GHDL.

tests/unit/test_ghdl_interface.py

Lines changed: 35 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -138,7 +138,31 @@ def test_assertion_on_unknown_backend(self, check_output):
138138
self.assertRaises(AssertionError, GHDLInterface.determine_backend, "prefix")
139139

140140
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") # pylint: disable=no-self-use
141-
def test_compile_project_2008(self, check_output):
141+
@mock.patch.object(GHDLInterface, "determine_version", return_value=6.0)
142+
def test_compile_project_2019(self, determine_version, check_output):
143+
simif = GHDLInterface(prefix="prefix", output_path="")
144+
write_file("file.vhd", "")
145+
146+
project = Project()
147+
project.add_library("lib", "lib_path")
148+
project.add_source_file("file.vhd", "lib", file_type="vhdl", vhdl_standard=VHDL.standard("2019"))
149+
simif.compile_project(project)
150+
check_output.assert_called_once_with(
151+
[
152+
str(Path("prefix") / "ghdl"),
153+
"-a",
154+
"--workdir=lib_path",
155+
"--work=lib",
156+
"--std=19",
157+
"-Plib_path",
158+
"file.vhd",
159+
],
160+
env=simif.get_env(),
161+
)
162+
163+
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") # pylint: disable=no-self-use
164+
@mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
165+
def test_compile_project_2008(self, determine_version, check_output):
142166
simif = GHDLInterface(prefix="prefix", output_path="")
143167
write_file("file.vhd", "")
144168

@@ -160,7 +184,8 @@ def test_compile_project_2008(self, check_output):
160184
)
161185

162186
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") # pylint: disable=no-self-use
163-
def test_compile_project_2002(self, check_output):
187+
@mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
188+
def test_compile_project_2002(self, determine_version, check_output):
164189
simif = GHDLInterface(prefix="prefix", output_path="")
165190
write_file("file.vhd", "")
166191

@@ -182,7 +207,8 @@ def test_compile_project_2002(self, check_output):
182207
)
183208

184209
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") # pylint: disable=no-self-use
185-
def test_compile_project_93(self, check_output):
210+
@mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
211+
def test_compile_project_93(self, determine_version, check_output):
186212
simif = GHDLInterface(prefix="prefix", output_path="")
187213
write_file("file.vhd", "")
188214

@@ -204,7 +230,8 @@ def test_compile_project_93(self, check_output):
204230
)
205231

206232
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="") # pylint: disable=no-self-use
207-
def test_compile_project_extra_flags(self, check_output):
233+
@mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
234+
def test_compile_project_extra_flags(self, determine_version, check_output):
208235
simif = GHDLInterface(prefix="prefix", output_path="")
209236
write_file("file.vhd", "")
210237

@@ -228,7 +255,8 @@ def test_compile_project_extra_flags(self, check_output):
228255
env=simif.get_env(),
229256
)
230257

231-
def test_elaborate_e_project(self):
258+
@mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
259+
def test_elaborate_e_project(self, determine_version):
232260
design_unit = Entity("tb_entity", file_name=str(Path("tempdir") / "file.vhd"))
233261
design_unit.original_file_name = str(Path("tempdir") / "other_path" / "original_file.vhd")
234262
design_unit.generic_names = ["runner_cfg", "tb_path"]
@@ -258,7 +286,8 @@ def test_elaborate_e_project(self):
258286
],
259287
)
260288

261-
def test_compile_project_verilog_error(self):
289+
@mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
290+
def test_compile_project_verilog_error(self, determine_version):
262291
simif = GHDLInterface(prefix="prefix", output_path="")
263292
write_file("file.v", "")
264293

vunit/builtins.py

Lines changed: 6 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -448,11 +448,10 @@ def _add_osvvm(self):
448448

449449
library.add_source_files(file_name, preprocessors=[])
450450

451-
def _add_vhdl_logging(self):
451+
def _add_vhdl_logging(self, use_external_log):
452452
"""
453453
Add logging functionality
454454
"""
455-
456455
use_call_paths = self._simulator_class.supports_vhdl_call_paths() and (
457456
self._vhdl_standard in VHDL.STD_2019.and_later
458457
)
@@ -467,6 +466,10 @@ def _add_vhdl_logging(self):
467466
if base_file_name.startswith("location_pkg-body"):
468467
continue
469468

469+
if (base_file_name == "common_log_pkg-body.vhd") and use_external_log:
470+
self._add_files(Path(use_external_log))
471+
continue
472+
470473
standards = set()
471474
for standard in VHDL.STANDARDS:
472475
standard_name = str(standard)
@@ -504,7 +507,7 @@ def add_vhdl_builtins(self, external=None, use_external_log=None):
504507
})
505508
"""
506509
self._add_data_types(external=external)
507-
self._add_vhdl_logging()
510+
self._add_vhdl_logging(use_external_log)
508511
self._add_files(VHDL_PATH / "*.vhd")
509512
for path in (
510513
"core",
@@ -516,14 +519,6 @@ def add_vhdl_builtins(self, external=None, use_external_log=None):
516519
):
517520
self._add_files(VHDL_PATH / path / "src" / "*.vhd")
518521

519-
logging_files = glob(str(VHDL_PATH / "logging" / "src" / "*.vhd"))
520-
for logging_file in logging_files:
521-
if logging_file.endswith("common_log_pkg-body.vhd") and use_external_log:
522-
self._add_files(Path(use_external_log))
523-
continue
524-
525-
self._add_files(Path(logging_file))
526-
527522

528523
def osvvm_is_installed():
529524
"""

vunit/sim_if/ghdl.py

Lines changed: 16 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -119,6 +119,7 @@ def __init__( # pylint: disable=too-many-arguments
119119
self._vhdl_standard = None
120120
self._coverage_test_dirs = set() # For gcov
121121
self._coverage_files = set() # For --coverage
122+
self._version = self.determine_version(self.find_prefix())
122123

123124
def has_valid_exit_code(self): # pylint: disable=arguments-differ
124125
"""
@@ -184,6 +185,13 @@ def determine_version(cls, prefix):
184185
).group(1)
185186
)
186187

188+
@classmethod
189+
def supports_vhdl_call_paths(cls):
190+
"""
191+
Returns True when this simulator supports VHDL-2019 call paths
192+
"""
193+
return False
194+
187195
@classmethod
188196
def supports_vhdl_package_generics(cls):
189197
"""
@@ -246,17 +254,21 @@ def compile_source_file_command(self, source_file):
246254
LOGGER.error("Unknown file type: %s", source_file.file_type)
247255
raise CompileError
248256

249-
@staticmethod
250-
def _std_str(vhdl_standard):
257+
def _std_str(self, vhdl_standard):
251258
"""
252259
Convert standard to format of GHDL command line flag
253260
"""
254-
if vhdl_standard == VHDL.STD_2002:
255-
return "02"
261+
if vhdl_standard == VHDL.STD_2019:
262+
if self._version >= 6.0:
263+
return "19"
264+
raise ValueError("VHDL-2019 requires GHDL >=6.0.0.")
256265

257266
if vhdl_standard == VHDL.STD_2008:
258267
return "08"
259268

269+
if vhdl_standard == VHDL.STD_2002:
270+
return "02"
271+
260272
if vhdl_standard == VHDL.STD_1993:
261273
return "93"
262274

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