Enabled VHDL-2019 for GHDL >= 6.0.0.

Note that VUnit log location support based on call_path is deactivated as this is yet to be supported by GHDL.

Author: LarsAsplund

docs/news.d/1177.feature.rst

@@ -0,0 +1,3 @@
+Enabled VHDL-2019 for GHDL >= 6.0.0.
+
+Note that VUnit log location support based on call_path is deactivated as this is yet to be supported by GHDL.

tests/unit/test_ghdl_interface.py

@@ -138,7 +138,8 @@ def test_assertion_on_unknown_backend(self, check_output):
         self.assertRaises(AssertionError, GHDLInterface.determine_backend, "prefix")
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")  # pylint: disable=no-self-use
-    def test_compile_project_2008(self, check_output):
+    @mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
+    def test_compile_project_2008(self, determine_version, check_output):
         simif = GHDLInterface(prefix="prefix", output_path="")
         write_file("file.vhd", "")
 
@@ -160,7 +161,8 @@ def test_compile_project_2008(self, check_output):
         )
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")  # pylint: disable=no-self-use
-    def test_compile_project_2002(self, check_output):
+    @mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
+    def test_compile_project_2002(self, determine_version, check_output):
         simif = GHDLInterface(prefix="prefix", output_path="")
         write_file("file.vhd", "")
 
@@ -182,7 +184,8 @@ def test_compile_project_2002(self, check_output):
         )
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")  # pylint: disable=no-self-use
-    def test_compile_project_93(self, check_output):
+    @mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
+    def test_compile_project_93(self, determine_version, check_output):
         simif = GHDLInterface(prefix="prefix", output_path="")
         write_file("file.vhd", "")
 
@@ -204,7 +207,8 @@ def test_compile_project_93(self, check_output):
         )
 
     @mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")  # pylint: disable=no-self-use
-    def test_compile_project_extra_flags(self, check_output):
+    @mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
+    def test_compile_project_extra_flags(self, determine_version, check_output):
         simif = GHDLInterface(prefix="prefix", output_path="")
         write_file("file.vhd", "")
 
@@ -228,7 +232,8 @@ def test_compile_project_extra_flags(self, check_output):
             env=simif.get_env(),
         )
 
-    def test_elaborate_e_project(self):
+    @mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
+    def test_elaborate_e_project(self, determine_version):
         design_unit = Entity("tb_entity", file_name=str(Path("tempdir") / "file.vhd"))
         design_unit.original_file_name = str(Path("tempdir") / "other_path" / "original_file.vhd")
         design_unit.generic_names = ["runner_cfg", "tb_path"]
@@ -258,7 +263,8 @@ def test_elaborate_e_project(self):
             ],
         )
 
-    def test_compile_project_verilog_error(self):
+    @mock.patch.object(GHDLInterface, "determine_version", return_value=5.0)
+    def test_compile_project_verilog_error(self, determine_version):
         simif = GHDLInterface(prefix="prefix", output_path="")
         write_file("file.v", "")
 

vunit/builtins.py

@@ -448,11 +448,10 @@ def _add_osvvm(self):
 
             library.add_source_files(file_name, preprocessors=[])
 
-    def _add_vhdl_logging(self):
+    def _add_vhdl_logging(self, use_external_log):
         """
         Add logging functionality
         """
-
         use_call_paths = self._simulator_class.supports_vhdl_call_paths() and (
             self._vhdl_standard in VHDL.STD_2019.and_later
         )
@@ -467,6 +466,10 @@ def _add_vhdl_logging(self):
             if base_file_name.startswith("location_pkg-body"):
                 continue
 
+            if (base_file_name == "common_log_pkg-body.vhd") and use_external_log:
+                self._add_files(Path(use_external_log))
+                continue
+
             standards = set()
             for standard in VHDL.STANDARDS:
                 standard_name = str(standard)
@@ -504,7 +507,7 @@ def add_vhdl_builtins(self, external=None, use_external_log=None):
             })
         """
         self._add_data_types(external=external)
-        self._add_vhdl_logging()
+        self._add_vhdl_logging(use_external_log)
         self._add_files(VHDL_PATH / "*.vhd")
         for path in (
             "core",
@@ -516,14 +519,6 @@ def add_vhdl_builtins(self, external=None, use_external_log=None):
         ):
             self._add_files(VHDL_PATH / path / "src" / "*.vhd")
 
-        logging_files = glob(str(VHDL_PATH / "logging" / "src" / "*.vhd"))
-        for logging_file in logging_files:
-            if logging_file.endswith("common_log_pkg-body.vhd") and use_external_log:
-                self._add_files(Path(use_external_log))
-                continue
-
-            self._add_files(Path(logging_file))
-
 
 def osvvm_is_installed():
     """

vunit/sim_if/ghdl.py

@@ -119,6 +119,7 @@ def __init__(  # pylint: disable=too-many-arguments
         self._vhdl_standard = None
         self._coverage_test_dirs = set()  # For gcov
         self._coverage_files = set()  # For --coverage
+        self._version = self.determine_version(self.find_prefix())
 
     def has_valid_exit_code(self):  # pylint: disable=arguments-differ
         """
@@ -184,6 +185,13 @@ def determine_version(cls, prefix):
             ).group(1)
         )
 
+    @classmethod
+    def supports_vhdl_call_paths(cls):
+        """
+        Returns True when this simulator supports VHDL-2019 call paths
+        """
+        return False
+
     @classmethod
     def supports_vhdl_package_generics(cls):
         """
@@ -246,17 +254,21 @@ def compile_source_file_command(self, source_file):
         LOGGER.error("Unknown file type: %s", source_file.file_type)
         raise CompileError
 
-    @staticmethod
-    def _std_str(vhdl_standard):
+    def _std_str(self, vhdl_standard):
         """
         Convert standard to format of GHDL command line flag
         """
-        if vhdl_standard == VHDL.STD_2002:
-            return "02"
+        if vhdl_standard == VHDL.STD_2019:
+            if self._version >= 6.0:
+                return "19"
+            raise ValueError("VHDL-2019 requires GHDL >=6.0.0.")
 
         if vhdl_standard == VHDL.STD_2008:
             return "08"
 
+        if vhdl_standard == VHDL.STD_2002:
+            return "02"
+
         if vhdl_standard == VHDL.STD_1993:
             return "93"