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Moved vhdl/verilog into vunit package folder
1 parent eeb6e09 commit c55b8ce

151 files changed

Lines changed: 79 additions & 75 deletions

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‎README.md‎

Lines changed: 3 additions & 3 deletions

‎examples/vhdl/check/compile.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6,13 +6,13 @@
66

77
from os.path import join, dirname
88
from vunit import VUnit
9-
from vunit import ROOT
9+
from vunit.builtins import VHDL_PATH
1010

1111
ui = VUnit.from_argv()
1212
ui.enable_check_preprocessing()
1313
lib = ui.add_library("lib")
1414
lib.add_source_files(join(dirname(__file__), "check_example.vhd"))
15-
common_path = join(ROOT, 'vhdl', 'common', 'test')
15+
common_path = join(VHDL_PATH, 'common', 'test')
1616
lib.add_source_files(join(common_path, "test_type_methods_api.vhd"))
1717
lib.add_source_files(join(common_path, "test_types200x.vhd"))
1818
lib.add_source_files(join(common_path, "test_type_methods200x.vhd"))

‎setup.py‎

Lines changed: 14 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -4,28 +4,30 @@
44
#
55
# Copyright (c) 2015, Lars Asplund lars.anders.asplund@gmail.com
66

7-
from distutils.core import setup
7+
from setuptools import setup
88
import os
99

1010

11-
def find_all_files(directory):
11+
def find_all_files(directory, endings=None):
1212
"""
1313
Recursively find all files within directory
1414
"""
1515
result = []
1616
for root, dirnames, filenames in os.walk(directory):
1717
for filename in filenames:
18-
result.append(os.path.join(root, filename))
18+
ending = os.path.splitext(filename)[-1]
19+
if endings is None or ending in endings:
20+
result.append(os.path.join(root, filename))
21+
else:
22+
print("Ignoring %s" % filename)
1923
return result
2024

21-
data_files = (find_all_files('vhdl') +
22-
find_all_files('verilog'))
23-
24-
# Makes data folder appear one directory level up from the vunit package in the installed system folder.
25-
# This is required since references are made with the source directory layout in mind
26-
# @TODO This is not very nice and could potentially cause problems,
27-
# we should move the data folders into the vunit package folder to keep locality
28-
data_files = [os.path.join("..", i) for i in data_files]
25+
data_files = []
26+
data_files += find_all_files(os.path.join('vunit', 'vhdl'),
27+
endings=[".vhd"])
28+
data_files += find_all_files(os.path.join('vunit', 'verilog'),
29+
endings=[".v", ".sv", ".svh"])
30+
data_files = [os.path.relpath(file_name, 'vunit') for file_name in data_files]
2931

3032
setup(
3133
name='vunit_hdl',
@@ -39,6 +41,7 @@ def find_all_files(directory):
3941
'vunit.test.unit',
4042
'vunit.test.acceptance'],
4143
package_data={'vunit': data_files},
44+
zip_safe=False,
4245
url='https://github.com/LarsAsplund/vunit',
4346
classifiers=['Development Status :: 5 - Production/Stable',
4447
'License :: OSI Approved :: Mozilla Public License 2.0 (MPL 2.0)',

‎user_guide.md‎

Lines changed: 3 additions & 3 deletions

‎vunit/builtins.py‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -12,8 +12,8 @@
1212
from os.path import join, abspath, dirname, basename
1313
from glob import glob
1414

15-
VHDL_PATH = abspath(join(dirname(__file__), "..", "vhdl"))
16-
VERILOG_PATH = abspath(join(dirname(__file__), "..", "verilog"))
15+
VHDL_PATH = abspath(join(dirname(__file__), "vhdl"))
16+
VERILOG_PATH = abspath(join(dirname(__file__), "verilog"))
1717

1818

1919
def add_verilog_builtins(library):

‎vunit/test/acceptance/test_external_run_scripts.py‎

Lines changed: 22 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@
1515
from subprocess import call
1616
import sys
1717
from vunit import ROOT
18+
from vunit.builtins import VHDL_PATH
1819
from os import environ
1920

2021

@@ -88,91 +89,91 @@ def test_vhdl_com_example_project(self):
8889
self.check(join(ROOT, "examples", "vhdl", "com", "run.py"))
8990

9091
def test_array_vhdl_2008(self):
91-
self.check(join(ROOT, "vhdl", "array", "run.py"))
92+
self.check(join(VHDL_PATH, "array", "run.py"))
9293

9394
def test_check_vhdl_2008(self):
94-
self.check(join(ROOT, "vhdl", "check", "run.py"))
95+
self.check(join(VHDL_PATH, "check", "run.py"))
9596

9697
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
9798
def test_check_vhdl_2002(self):
98-
self.check(join(ROOT, "vhdl", "check", "run.py"),
99+
self.check(join(VHDL_PATH, "check", "run.py"),
99100
vhdl_standard='2002')
100101

101102
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
102103
def test_check_vhdl_93(self):
103-
self.check(join(ROOT, "vhdl", "check", "run.py"),
104+
self.check(join(VHDL_PATH, "check", "run.py"),
104105
vhdl_standard='93')
105106

106107
def test_logging_vhdl_2008(self):
107-
self.check(join(ROOT, "vhdl", "logging", "run.py"))
108+
self.check(join(VHDL_PATH, "logging", "run.py"))
108109

109110
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
110111
def test_logging_vhdl_2002(self):
111-
self.check(join(ROOT, "vhdl", "logging", "run.py"),
112+
self.check(join(VHDL_PATH, "logging", "run.py"),
112113
vhdl_standard='2002')
113114

114115
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
115116
def test_logging_vhdl_93(self):
116-
self.check(join(ROOT, "vhdl", "logging", "run.py"),
117+
self.check(join(VHDL_PATH, "logging", "run.py"),
117118
vhdl_standard='93')
118119

119120
def test_run_vhdl_2008(self):
120-
self.check(join(ROOT, "vhdl", "run", "run.py"))
121+
self.check(join(VHDL_PATH, "run", "run.py"))
121122

122123
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
123124
def test_run_vhdl_2002(self):
124-
self.check(join(ROOT, "vhdl", "run", "run.py"),
125+
self.check(join(VHDL_PATH, "run", "run.py"),
125126
vhdl_standard='2002')
126127

127128
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
128129
def test_run_vhdl_93(self):
129-
self.check(join(ROOT, "vhdl", "run", "run.py"),
130+
self.check(join(VHDL_PATH, "run", "run.py"),
130131
vhdl_standard='93')
131132

132133
def test_string_ops_vhdl_2008(self):
133-
self.check(join(ROOT, "vhdl", "string_ops", "run.py"))
134+
self.check(join(VHDL_PATH, "string_ops", "run.py"))
134135

135136
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
136137
def test_string_ops_vhdl_2002(self):
137-
self.check(join(ROOT, "vhdl", "string_ops", "run.py"),
138+
self.check(join(VHDL_PATH, "string_ops", "run.py"),
138139
vhdl_standard='2002')
139140

140141
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
141142
def test_string_ops_vhdl_93(self):
142-
self.check(join(ROOT, "vhdl", "string_ops", "run.py"),
143+
self.check(join(VHDL_PATH, "string_ops", "run.py"),
143144
vhdl_standard='93')
144145

145146
def test_dictionary_vhdl_2008(self):
146-
self.check(join(ROOT, "vhdl", "dictionary", "run.py"))
147+
self.check(join(VHDL_PATH, "dictionary", "run.py"))
147148

148149
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
149150
def test_dictionary_vhdl_2002(self):
150-
self.check(join(ROOT, "vhdl", "dictionary", "run.py"),
151+
self.check(join(VHDL_PATH, "dictionary", "run.py"),
151152
vhdl_standard='2002')
152153

153154
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
154155
def test_dictionary_vhdl_93(self):
155-
self.check(join(ROOT, "vhdl", "dictionary", "run.py"),
156+
self.check(join(VHDL_PATH, "dictionary", "run.py"),
156157
vhdl_standard='93')
157158

158159
def test_path_vhdl_2008(self):
159-
self.check(join(ROOT, "vhdl", "path", "run.py"))
160+
self.check(join(VHDL_PATH, "path", "run.py"))
160161

161162
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
162163
def test_path_vhdl_2002(self):
163-
self.check(join(ROOT, "vhdl", "path", "run.py"),
164+
self.check(join(VHDL_PATH, "path", "run.py"),
164165
vhdl_standard='2002')
165166

166167
@unittest.skipUnless(simulator_is("modelsim"), "Only 2008 support")
167168
def test_path_vhdl_93(self):
168-
self.check(join(ROOT, "vhdl", "path", "run.py"),
169+
self.check(join(VHDL_PATH, "path", "run.py"),
169170
vhdl_standard='93')
170171

171172
def test_com_vhdl_2008(self):
172-
self.check(join(ROOT, "vhdl", "com", "run.py"))
173+
self.check(join(VHDL_PATH, "com", "run.py"))
173174

174175
def test_com_debug_vhdl_2008(self):
175-
self.check(join(ROOT, "vhdl", "com", "run.py"),
176+
self.check(join(VHDL_PATH, "com", "run.py"),
176177
args=["--use-debug-codecs"])
177178

178179
def test_vhdl_compile_order_project(self):

‎vunit/test/lint/test_license.py‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@
1616
from datetime import datetime
1717
from subprocess import Popen, PIPE, STDOUT
1818
from vunit import ROOT
19+
from vunit.builtins import VHDL_PATH
1920
import vunit.ostools as ostools
2021

2122

@@ -34,7 +35,7 @@ def test_that_a_valid_license_exists_in_source_files_and_that_global_licensing_i
3435
continue
3536
if 'codecs' in root:
3637
continue
37-
osvvm_directory = abspath(join(ROOT, 'vhdl', 'osvvm'))
38+
osvvm_directory = abspath(join(VHDL_PATH, 'osvvm'))
3839
if is_prefix_of(osvvm_directory, abspath(join(root, file_name))):
3940
continue
4041
osvvm_integration_example_directory = abspath(

verilog/include/vunit_defines.svh renamed to vunit/verilog/include/vunit_defines.svh

File renamed without changes.

verilog/vunit_pkg.sv renamed to vunit/verilog/vunit_pkg.sv

File renamed without changes.

vhdl/array/run.py renamed to vunit/vhdl/array/run.py

File renamed without changes.

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