Added modelsim_vcom_flags and modelsim_vlog_flags compile options #97

Author: kraigher

user_guide.md

@@ -328,6 +328,10 @@ vu.set_compile_option("ghdl_flags", ["--no-vital-checks"])
 * `ghdl_flags`
   - Extra arguments passed to `ghdl -a` command. Must be a list of strings.
   - Example `vu.set_compile_option("ghdl_flags", ["--no-vital-checks"])`.
+* `modelsim_vcom_flags`
+  - Extra arguments passed to ModelSim `vcom` command. Must be a list of strings.
+* `modelsim_vlog_flags`
+  - Extra arguments passed to ModelSim `vlog` command. Must be a list of strings.
 
 ## Ctrl-C when using Git/MSYS Bash on Windows
 VUnit will catch Ctrl-C and perform a clean shutdown closing all started simulation processes and printing the test report so far. On Git/MSYS Bash on Windows however there is a mechanism that hard kills a process a very short time after pressing Ctrl-C often prohibiting VUnit from completing its shutdown. This can leave simulation process open which have to be manually killed. See this [stack overflow post](http://stackoverflow.com/questions/23678045/control-c-kills-ipython-in-git-bash-on-windows-7) for tips on how to remove this mechanism.

vunit/modelsim_interface.py

@@ -2,7 +2,7 @@
 # License, v. 2.0. If a copy of the MPL was not distributed with this file,
 # You can obtain one at http://mozilla.org/MPL/2.0/.
 #
-# Copyright (c) 2014-2015, Lars Asplund lars.anders.asplund@gmail.com
+# Copyright (c) 2014-2016, Lars Asplund lars.anders.asplund@gmail.com
 
 """
 Interface towards Mentor Graphics ModelSim
@@ -173,19 +173,23 @@ def compile_project(self, project, vhdl_standard):
             print('Compiling ' + source_file.name + ' into ' + source_file.library.name + ' ...')
 
             if source_file.file_type == 'vhdl':
-                success = self.compile_vhdl_file(source_file.name, source_file.library.name, vhdl_standard)
+                success = self.compile_vhdl_file(source_file.name,
+                                                 source_file.library.name,
+                                                 vhdl_standard,
+                                                 source_file.compile_options)
             elif source_file.file_type == 'verilog':
                 success = self.compile_verilog_file(source_file.name,
                                                     source_file.library.name,
-                                                    source_file.include_dirs)
+                                                    source_file.include_dirs,
+                                                    source_file.compile_options)
             else:
                 raise RuntimeError("Unkown file type: " + source_file.file_type)
 
             if not success:
                 raise CompileError("Failed to compile '%s'" % source_file.name)
             project.update(source_file)
 
-    def compile_vhdl_file(self, source_file_name, library_name, vhdl_standard):
+    def compile_vhdl_file(self, source_file_name, library_name, vhdl_standard, compile_options):
         """
         Compiles a vhdl file into a specific library using a specfic vhdl_standard
         """
@@ -196,15 +200,15 @@ def compile_vhdl_file(self, source_file_name, library_name, vhdl_standard):
                 coverage_args = ["+cover=" + to_coverage_args(self._coverage)]
 
             proc = Process([join(self._prefix, 'vcom'), '-quiet', '-modelsimini', self._modelsim_ini] +
-                           coverage_args +
+                           coverage_args + compile_options.get("modelsim_vcom_flags", []) +
                            ['-' + vhdl_standard, '-work', library_name, source_file_name])
 
             proc.consume_output()
         except Process.NonZeroExitCode:
             return False
         return True
 
-    def compile_verilog_file(self, source_file_name, library_name, include_dirs):
+    def compile_verilog_file(self, source_file_name, library_name, include_dirs, compile_options):
         """
         Compiles a verilog file into a specific library
         """
@@ -216,6 +220,7 @@ def compile_verilog_file(self, source_file_name, library_name, include_dirs):
 
             args = [join(self._prefix, 'vlog'), '-sv', '-quiet', '-modelsimini', self._modelsim_ini]
             args += coverage_args
+            args += compile_options.get("modelsim_vlog_flags", [])
             args += ['-work', library_name, source_file_name]
 
             for library in self._libraries.values():

vunit/project.py

@@ -561,7 +561,9 @@ def __hash__(self):
     def __repr__(self):
         return "SourceFile(%s, %s)" % (self.name, self.library.name)
 
-    _allowed_compile_options = ["ghdl_flags"]
+    _allowed_compile_options = ["ghdl_flags",
+                                "modelsim_vcom_flags",
+                                "modelsim_vlog_flags"]
 
     def set_compile_option(self, name, value):
         """