Issue #85. Ignoring type generics

Author: kraigher

vunit/test/unit/test_vhdl_parser.py

@@ -53,6 +53,21 @@ def test_parsing_entity_with_package_generic(self):
         self.assertEqual(entity.generics[0].identifier, 'package_g')
         self.assertEqual(entity.generics[0].subtype_indication.type_mark, 'integer')
 
+    def test_parsing_entity_with_type_generic(self):
+        entity = self.parse_single_entity("""\
+entity ent is
+  generic (
+    type t;
+    type_g : integer
+    );
+end entity;
+""")
+        self.assertEqual(entity.identifier, "ent")
+        self.assertEqual(entity.ports, [])
+        self.assertEqual(len(entity.generics), 1)
+        self.assertEqual(entity.generics[0].identifier, 'type_g')
+        self.assertEqual(entity.generics[0].subtype_indication.type_mark, 'integer')
+
     def test_getting_entities_from_design_file(self):
         design_file = VHDLDesignFile.parse("""
 entity entity1 is

vunit/vhdl_parser.py

@@ -397,6 +397,7 @@ def _find_port_clause(cls, code):
         return []
 
     _package_generic_re = re.compile(r"\s*package\s+", re.MULTILINE | re.IGNORECASE)
+    _type_generic_re = re.compile(r"\s*type\s+", re.MULTILINE | re.IGNORECASE)
 
     @classmethod
     def _parse_generic_clause(cls, code):
@@ -413,10 +414,14 @@ def _parse_generic_clause(cls, code):
         # Add interface elements to the generic list
         for interface_element in interface_elements:
 
-            if cls._package_generic_re.match(interface_element.strip()) is not None:
+            if cls._package_generic_re.match(interface_element) is not None:
                 # Ignore package generics
                 continue
 
+            if cls._type_generic_re.match(interface_element) is not None:
+                # Ignore type generics
+                continue
+
             generic_list.append(VHDLInterfaceElement.parse(interface_element))
 
         return generic_list