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LarsAsplundLarsAsplund
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Enabled VHDL-2019 and added support for new -ini flag in Questa.
1 parent 4090eb5 commit b5b8cc2

3 files changed

Lines changed: 92 additions & 55 deletions

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‎tests/unit/test_modelsim_interface.py‎

Lines changed: 31 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -27,9 +27,10 @@ class TestModelSimInterface(unittest.TestCase):
2727
Test the ModelSim interface
2828
"""
2929

30+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
3031
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
3132
@mock.patch("vunit.sim_if.modelsim.Process", autospec=True)
32-
def test_compile_project_vhdl_2008(self, process, check_output):
33+
def test_compile_project_vhdl_2008(self, process, sim_check_output, modelsim_check_output):
3334
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
3435
project = Project()
3536
project.add_library("lib", "lib_path")
@@ -48,11 +49,12 @@ def test_compile_project_vhdl_2008(self, process, check_output):
4849
"lib",
4950
"file.vhd",
5051
]
51-
check_output.assert_called_once_with(check_args, env=simif.get_env())
52+
sim_check_output.assert_called_once_with(check_args, env=simif.get_env())
5253

54+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
5355
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
5456
@mock.patch("vunit.sim_if.modelsim.Process", autospec=True)
55-
def test_compile_project_vhdl_2002(self, process, check_output):
57+
def test_compile_project_vhdl_2002(self, process, check_output, modelsim_check_output):
5658
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
5759
project = Project()
5860
project.add_library("lib", "lib_path")
@@ -73,9 +75,10 @@ def test_compile_project_vhdl_2002(self, process, check_output):
7375
]
7476
check_output.assert_called_once_with(check_args, env=simif.get_env())
7577

78+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
7679
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
7780
@mock.patch("vunit.sim_if.modelsim.Process", autospec=True)
78-
def test_compile_project_vhdl_93(self, process, check_output):
81+
def test_compile_project_vhdl_93(self, process, check_output, modelsim_check_output):
7982
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
8083
project = Project()
8184
project.add_library("lib", "lib_path")
@@ -96,9 +99,10 @@ def test_compile_project_vhdl_93(self, process, check_output):
9699
]
97100
check_output.assert_called_once_with(check_args, env=simif.get_env())
98101

102+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
99103
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
100104
@mock.patch("vunit.sim_if.modelsim.Process", autospec=True)
101-
def test_compile_project_vhdl_extra_flags(self, process, check_output):
105+
def test_compile_project_vhdl_extra_flags(self, process, check_output, modelsim_check_output):
102106
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
103107
project = Project()
104108
project.add_library("lib", "lib_path")
@@ -122,9 +126,10 @@ def test_compile_project_vhdl_extra_flags(self, process, check_output):
122126
]
123127
check_output.assert_called_once_with(check_args, env=simif.get_env())
124128

129+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
125130
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
126131
@mock.patch("vunit.sim_if.modelsim.Process", autospec=True)
127-
def test_compile_project_verilog(self, process, check_output):
132+
def test_compile_project_verilog(self, process, check_output, modelsim_check_output):
128133
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
129134
project = Project()
130135
project.add_library("lib", "lib_path")
@@ -146,9 +151,10 @@ def test_compile_project_verilog(self, process, check_output):
146151
]
147152
check_output.assert_called_once_with(check_args, env=simif.get_env())
148153

154+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
149155
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
150156
@mock.patch("vunit.sim_if.modelsim.Process", autospec=True)
151-
def test_compile_project_system_verilog(self, process, check_output):
157+
def test_compile_project_system_verilog(self, process, check_output, modelsim_check_output):
152158
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
153159
project = Project()
154160
project.add_library("lib", "lib_path")
@@ -171,9 +177,10 @@ def test_compile_project_system_verilog(self, process, check_output):
171177
]
172178
check_output.assert_called_once_with(check_args, env=simif.get_env())
173179

180+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
174181
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
175182
@mock.patch("vunit.sim_if.modelsim.Process", autospec=True)
176-
def test_compile_project_verilog_extra_flags(self, process, check_output):
183+
def test_compile_project_verilog_extra_flags(self, process, check_output, modelsim_check_output):
177184
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
178185
project = Project()
179186
project.add_library("lib", "lib_path")
@@ -198,9 +205,10 @@ def test_compile_project_verilog_extra_flags(self, process, check_output):
198205
]
199206
check_output.assert_called_once_with(check_args, env=simif.get_env())
200207

208+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
201209
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
202210
@mock.patch("vunit.sim_if.modelsim.Process", autospec=True)
203-
def test_compile_project_verilog_include(self, process, check_output):
211+
def test_compile_project_verilog_include(self, process, check_output, modelsim_check_output):
204212
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
205213
project = Project()
206214
project.add_library("lib", "lib_path")
@@ -223,9 +231,10 @@ def test_compile_project_verilog_include(self, process, check_output):
223231
]
224232
check_output.assert_called_once_with(check_args, env=simif.get_env())
225233

234+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
226235
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
227236
@mock.patch("vunit.sim_if.modelsim.Process", autospec=True)
228-
def test_compile_project_verilog_define(self, process, check_output):
237+
def test_compile_project_verilog_define(self, process, check_output, modelsim_check_output):
229238
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
230239
project = Project()
231240
project.add_library("lib", "lib_path")
@@ -255,7 +264,8 @@ def _get_inis(self):
255264
str(Path(self.test_path) / "my_modelsim.ini"),
256265
)
257266

258-
def test_copies_modelsim_ini_file_from_install(self):
267+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
268+
def test_copies_modelsim_ini_file_from_install(self, _check_output):
259269
(modelsim_ini, installed_modelsim_ini, user_modelsim_ini) = self._get_inis()
260270

261271
with open(installed_modelsim_ini, "w") as fptr:
@@ -268,7 +278,8 @@ def test_copies_modelsim_ini_file_from_install(self):
268278
with open(modelsim_ini, "r") as fptr:
269279
self.assertEqual(fptr.read(), "installed")
270280

271-
def test_copies_modelsim_ini_file_from_user(self):
281+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
282+
def test_copies_modelsim_ini_file_from_user(self, _check_output):
272283
(modelsim_ini, installed_modelsim_ini, user_modelsim_ini) = self._get_inis()
273284

274285
with open(installed_modelsim_ini, "w") as fptr:
@@ -283,7 +294,8 @@ def test_copies_modelsim_ini_file_from_user(self):
283294
with open(modelsim_ini, "r") as fptr:
284295
self.assertEqual(fptr.read(), "user")
285296

286-
def test_overwrites_modelsim_ini_file_from_install(self):
297+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
298+
def test_overwrites_modelsim_ini_file_from_install(self, _check_output):
287299
(modelsim_ini, installed_modelsim_ini, user_modelsim_ini) = self._get_inis()
288300

289301
with open(modelsim_ini, "w") as fptr:
@@ -299,7 +311,8 @@ def test_overwrites_modelsim_ini_file_from_install(self):
299311
with open(modelsim_ini, "r") as fptr:
300312
self.assertEqual(fptr.read(), "installed")
301313

302-
def test_overwrites_modelsim_ini_file_from_user(self):
314+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
315+
def test_overwrites_modelsim_ini_file_from_user(self, _check_output):
303316
(modelsim_ini, installed_modelsim_ini, user_modelsim_ini) = self._get_inis()
304317

305318
with open(modelsim_ini, "w") as fptr:
@@ -317,11 +330,14 @@ def test_overwrites_modelsim_ini_file_from_user(self):
317330
with open(modelsim_ini, "r") as fptr:
318331
self.assertEqual(fptr.read(), "user")
319332

333+
@mock.patch("vunit.sim_if.modelsim.check_output", autospec=True, return_value="")
320334
@mock.patch("vunit.sim_if.modelsim.LOGGER", autospec=True)
321335
@mock.patch("vunit.sim_if.check_output", autospec=True, return_value="")
322336
@mock.patch("vunit.sim_if.modelsim.Process", autospec=True)
323337
@mock.patch("vunit.sim_if.vsim_simulator_mixin.Process", autospec=True)
324-
def test_optimize(self, vsim_simulator_mixin_process, modelsim_process, check_output, LOGGER):
338+
def test_optimize(
339+
self, vsim_simulator_mixin_process, modelsim_process, check_output, LOGGER, modelsim_check_output
340+
):
325341
simif = ModelSimInterface(prefix=self.prefix_path, output_path=self.output_path, persistent=False)
326342
project = Project()
327343
project.add_library("lib", str(Path(self.libraries_path) / "lib"))

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