uart vc: add testbenches/test cases

Author: rafaelnp

examples/vhdl/uart/run.py

@@ -27,4 +27,14 @@
 VU.add_library("uart_lib").add_source_files(SRC_PATH / "*.vhd")
 VU.add_library("tb_uart_lib").add_source_files(SRC_PATH / "test" / "*.vhd")
 
+for tb in VU.library("tb_uart_lib").get_test_benches():
+    for parity in [0, 1, 2]:
+        generics = dict(
+            parity=parity
+        )
+        tb.add_config(
+            name=",".join("{}={}".format(k, v) for (k, v) in generics.items()),
+            generics=generics,
+        )
+
 VU.main()

examples/vhdl/uart/src/test/tb_uart_rx.vhd

@@ -16,7 +16,8 @@ library uart_lib;
 
 entity tb_uart_rx is
   generic (
-    runner_cfg : string);
+    runner_cfg : string;
+    parity : natural);
 end entity;
 
 architecture tb of tb_uart_rx is
@@ -33,7 +34,8 @@ architecture tb of tb_uart_rx is
 
   signal num_overflows : integer := 0;
 
-  constant uart_bfm : uart_master_t := new_uart_master(initial_baud_rate => baud_rate);
+  constant uart_bfm : uart_master_t := new_uart_master(initial_baud_rate => baud_rate,
+                                                       initial_parity => parity);
   constant uart_stream : stream_master_t := as_stream(uart_bfm);
 
   constant axi_stream_bfm : axi_stream_slave_t := new_axi_stream_slave(data_length => tdata'length);
@@ -87,7 +89,8 @@ begin
 
   dut : entity uart_lib.uart_rx
     generic map (
-      cycles_per_bit => cycles_per_bit)
+      cycles_per_bit => cycles_per_bit,
+      parity => parity)
     port map (
       clk => clk,
       rx => rx,

examples/vhdl/uart/src/test/tb_uart_tx.vhd

@@ -19,7 +19,8 @@ library uart_lib;
 
 entity tb_uart_tx is
   generic (
-    runner_cfg : string);
+    runner_cfg : string;
+    parity : natural);
 end entity;
 
 architecture tb of tb_uart_tx is
@@ -35,6 +36,7 @@ architecture tb of tb_uart_tx is
 
   shared variable rnd_stimuli, rnd_expected : RandomPType;
   constant uart_bfm : uart_slave_t := new_uart_slave(initial_baud_rate => baud_rate,
+                                                     initial_parity => parity,
                                                      data_length => tdata'length);
   constant uart_stream : stream_slave_t := as_stream(uart_bfm);
 
@@ -79,7 +81,8 @@ begin
 
   dut : entity uart_lib.uart_tx
     generic map (
-      cycles_per_bit => cycles_per_bit)
+      cycles_per_bit => cycles_per_bit,
+      parity => parity)
     port map (
       clk => clk,
       tx => tx,

examples/vhdl/uart/src/uart_rx.vhd

@@ -15,7 +15,8 @@ use vunit_lib.logger_pkg.all;
 
 entity uart_rx is
   generic (
-    cycles_per_bit : natural := 434);
+    cycles_per_bit : natural := 434;
+    parity : natural := 0);
   port (
    clk : in std_logic;
 
@@ -29,6 +30,7 @@ entity uart_rx is
    tvalid : out std_Logic := '0';
    tdata : out std_logic_vector(7 downto 0));
 begin
+
   -- pragma translate_off
   check_stable(clk, check_enabled, tvalid, tready, tdata, "tdata must be stable until tready is active");
   check_stable(clk, check_enabled, tvalid, tready, tvalid, "tvalid must be active until tready is active");
@@ -46,12 +48,30 @@ end entity;
 
 architecture a of uart_rx is
   signal tvalid_int : std_logic := '0';
+
+  function data_size(
+    constant parity: natural
+  ) return natural is
+  begin
+    if parity = 0 then
+      -- uart data (8 bits)
+      return 8;
+    elsif parity = 1 or parity = 2 then
+      -- uart data (8 bits)+ parity
+      return 9;
+    else
+      -- invalid mode
+      return 0;
+    end if;
+  end function data_size;
+
 begin
   main : process (clk)
     type state_t is (idle, receiving, done);
     variable state : state_t := idle;
+    variable datawidth : natural := data_size(parity);
     variable cycles : natural range 0 to cycles_per_bit-1 := 0;
-    variable data : std_logic_vector(7 downto 0);
+    variable data : std_logic_vector(datawidth-1 downto 0);
     variable index : natural range 0 to data'length-1 := 0;
   begin
     if rising_edge(clk) then
@@ -89,7 +109,7 @@ begin
           -- New output overwrites old output
           overflow <= tvalid_int and not tready;
           tvalid_int <= '1';
-          tdata <= data;
+          tdata <= data(7 downto 0);
           state := idle;
       end case;
 

examples/vhdl/uart/src/uart_tx.vhd

@@ -15,7 +15,8 @@ use vunit_lib.logger_pkg.all;
 
 entity uart_tx is
   generic (
-    cycles_per_bit : natural := 434);
+    cycles_per_bit : natural := 434;
+    parity : natural := 0);
   port (
    clk : in std_logic;
 
@@ -44,12 +45,42 @@ end entity;
 
 architecture a of uart_tx is
   signal tready_int : std_logic := '0';
+
+  function data_size(
+    constant parity: natural
+  ) return natural is
+  begin
+    if parity = 0 then
+      -- uart data (8 bits)
+      return 8;
+    elsif parity = 1 or parity = 2 then
+      -- uart data (8 bits)+ parity
+      return 9;
+    else
+      -- invalid mode
+      return 0;
+    end if;
+  end function data_size;
+
+  function even_parity (data : std_logic_vector) return std_logic is
+  begin
+    return xor data;
+
+  end function even_parity;
+
+  function odd_parity (data : std_logic_vector) return std_logic is
+  begin
+
+    return xnor data;
+  end function odd_parity;
+
 begin
   main : process (clk)
     type state_t is (idle, sending);
     variable state : state_t := idle;
+    variable datawidth : natural := data_size(parity) + 2;
     variable cycles : natural range 0 to cycles_per_bit-1 := 0;
-    variable data : std_logic_vector(9 downto 0);
+    variable data : std_logic_vector(datawidth-1 downto 0);
     variable index : natural range 0 to data'length-1 := 0;
   begin
     if rising_edge(clk) then
@@ -60,7 +91,14 @@ begin
             state := sending;
             cycles := 0;
             index := 0;
-            data := '1' & tdata & '0';
+
+            if parity = 0 then
+              data := '1' & tdata & '0';
+            elsif parity = 1 then
+              data := '1' & odd_parity(tdata) & tdata & '0';
+            elsif parity = 2 then
+              data := '1' & even_parity(tdata) & tdata & '0';
+            end if;
           end if;
         when sending =>
           tx <= data(0);

vunit/vhdl/verification_components/test/tb_uart.vhd

@@ -27,6 +27,12 @@ architecture a of tb_uart is
   constant slave_uart : uart_slave_t := new_uart_slave(data_length => 8);
   constant slave_stream : stream_slave_t := as_stream(slave_uart);
 
+  -- parity related VCs
+  constant master_uart_p : uart_master_t := new_uart_master;
+  constant master_stream_p : stream_master_t := as_stream(master_uart);
+
+  constant slave_uart_p : uart_slave_t := new_uart_slave(data_length => 8);
+  constant slave_stream_p : stream_slave_t := as_stream(slave_uart);
   signal chan : std_logic;
 begin
 
@@ -83,6 +89,28 @@ begin
       test_baud_rate(2000);
       test_baud_rate(7000);
       test_baud_rate(200000);
+    elsif run("test_parity_odd") then
+      set_parity(net, master_uart_p, 1);
+      set_parity(net, slave_uart_p, 1);
+
+      for i in 0 to 7 loop
+        push_stream(net, master_stream_p,
+                    std_logic_vector(to_unsigned(i+1, data'length)));
+        pop_stream(net, slave_stream_p, data);
+        check_equal(data, std_logic_vector(to_unsigned(i+1, data'length)), "pop stream data");
+      end loop;
+
+    elsif run("test_parity_even") then
+      set_parity(net, master_uart_p, 2);
+      set_parity(net, slave_uart_p, 2);
+
+      for i in 0 to 7 loop
+        push_stream(net, master_stream_p,
+                    std_logic_vector(to_unsigned(i+1, data'length)));
+        pop_stream(net, slave_stream_p, data);
+        check_equal(data, std_logic_vector(to_unsigned(i+1, data'length)), "pop stream data");
+      end loop;
+
     end if;
 
     test_runner_cleanup(runner);