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update license dates to 2021
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‎LICENSE.rst‎

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‎docs/conf.py‎

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master_doc = "index"
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project = u"VUnit"
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copyright = u"2014-2020, Lars Asplund"
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copyright = u"2014-2021, Lars Asplund"
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author = u"LarsAsplund, kraigher and contributors"
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version = ""

‎docs/contributing.rst‎

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‎examples/verilog/uart/run.py‎

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# License, v. 2.0. If a copy of the MPL was not distributed with this file,
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# You can obtain one at http://mozilla.org/MPL/2.0/.
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#
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# Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com
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# Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com
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"""
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SystemVerilog UART

‎examples/verilog/uart/src/test/tb_uart_rx.sv‎

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// License, v. 2.0. If a copy of the MPL was not distributed with this file,
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// You can obtain one at http://mozilla.org/MPL/2.0/.
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//
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// Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com
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// Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com
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`include "vunit_defines.svh"
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‎examples/verilog/uart/src/test/tb_uart_tx.sv‎

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// License, v. 2.0. If a copy of the MPL was not distributed with this file,
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// You can obtain one at http://mozilla.org/MPL/2.0/.
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//
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// Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com
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// Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com
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`include "vunit_defines.svh"
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‎examples/verilog/uart/src/uart_rx.sv‎

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// License, v. 2.0. If a copy of the MPL was not distributed with this file,
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// You can obtain one at http://mozilla.org/MPL/2.0/.
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//
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// Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com
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// Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com
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module uart_rx(clk, rx, overflow, tready, tvalid, tdata);
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parameter integer cycles_per_bit = 434;

‎examples/verilog/uart/src/uart_tx.sv‎

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// License, v. 2.0. If a copy of the MPL was not distributed with this file,
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// You can obtain one at http://mozilla.org/MPL/2.0/.
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//
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// Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com
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// Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com
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module uart_tx(clk, tx, tready, tvalid, tdata);
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parameter integer cycles_per_bit = 434;

‎examples/verilog/user_guide/run.py‎

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# License, v. 2.0. If a copy of the MPL was not distributed with this file,
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# You can obtain one at http://mozilla.org/MPL/2.0/.
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#
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# Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com
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# Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com
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"""
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SystemVerilog User Guide

‎examples/verilog/user_guide/tb_example.sv‎

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// License, v. 2.0. If a copy of the MPL was not distributed with this file,
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// You can obtain one at http://mozilla.org/MPL/2.0/.
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//
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// Copyright (c) 2014-2020, Lars Asplund lars.anders.asplund@gmail.com
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// Copyright (c) 2014-2021, Lars Asplund lars.anders.asplund@gmail.com
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// You do not need to worry about adding vunit_defines.svh to your
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// include path, VUnit will automatically do that for you if VUnit is

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