Refactoring

Author: LarsAsplund

vunit/vhdl/verification_components/src/axi_stream_master.vhd

@@ -99,14 +99,6 @@ begin
     variable axi_stream_signal : axi_stream_signal_t;
     variable stall_config : integer_vector_ptr_t;
 
-    procedure probability_stall_axi_stream(
-      signal aclk : in std_logic;
-      axi_stream  : in axi_stream_master_t;
-      rnd         : inout RandomPType) is
-    begin
-      probability_stall_axi_stream(aclk, get_stall_config(axi_stream), rnd);
-    end procedure;
-
     procedure drive_inactive(
       signal l_tdata : out std_logic_vector(data_length(master)-1 downto 0);
       signal l_tlast : out std_logic;
@@ -159,7 +151,7 @@ begin
     rnd.InitSeed(rnd'instance_name);
     loop
       drive_inactive(tdata, tlast, tkeep, tstrb, tid, tdest, tuser);
-      if (areset_n = '0') then
+      if areset_n = '0' then
         tvalid <= '0';
         wait until areset_n = '1' and rising_edge(aclk);
       else
@@ -182,7 +174,7 @@ begin
 
           elsif msg_type = stream_push_msg or msg_type = push_axi_stream_msg then
             -- stall according to probability configuration
-            probability_stall_axi_stream(aclk, master, rnd);
+            probability_stall_axi_stream(aclk, get_stall_config(master), rnd);
 
             tvalid <= '1';
             tdata <= pop_std_ulogic_vector(msg);
@@ -194,11 +186,7 @@ begin
               tdest <= pop_std_ulogic_vector(msg);
               tuser <= pop_std_ulogic_vector(msg);
             else
-              if pop_boolean(msg) then
-                tlast <= '1';
-              else
-                tlast <= '0';
-              end if;
+              tlast <= '1' when pop_boolean(msg) else '0';
               tkeep <= (others => '1');
               tstrb <= (others => '1');
               tid   <= (others => '0');

vunit/vhdl/verification_components/src/axi_stream_monitor.vhd

@@ -8,6 +8,7 @@ library ieee;
 use ieee.std_logic_1164.all;
 
 use work.axi_stream_pkg.all;
+use work.axi_stream_private_pkg.all;
 use work.com_pkg.net;
 use work.com_pkg.publish;
 use work.com_types_pkg.msg_t;
@@ -55,7 +56,7 @@ begin
       );
     end if;
 
-    tstrb_resolved := tkeep when is_u(tstrb) else tstrb;
+    tstrb_resolved := resolve_tstrb(tkeep, tstrb);
     axi_stream_transaction := (
       tdata => tdata,
       tlast => tlast = '1',

vunit/vhdl/verification_components/src/axi_stream_pkg.vhd

@@ -397,16 +397,16 @@ package axi_stream_pkg is
     max_stall_cycles  : natural
   ) return stall_config_t;
 
-  function is_u(value : std_ulogic_vector) return boolean;
-
   -- Private
   constant p_stall_config_idx : natural := 0;
-  constant p_interactive_policy_idx : natural := 1;
+  constant p_inactive_policy_idx : natural := 1;
   impure function p_to_stall_config(vec : integer_vector_ptr_t) return stall_config_t;
 
 end package;
 
 package body axi_stream_pkg is
+  constant single_precision_mantissa_length : natural := 23;
+
   impure function get_valid_monitor(
     data_length      : natural;
     id_length        : natural  := 0;
@@ -472,19 +472,19 @@ package body axi_stream_pkg is
         axi_stream_checker,
         protocol_checker.p_id_length,
         id_length,
-        "ID length of monitor doesn't match that of the " & parent_component
+        "ID length of protocol checker doesn't match that of the " & parent_component
       );
       check_equal(
         axi_stream_checker,
         protocol_checker.p_dest_length,
         dest_length,
-        "Dest length of monitor doesn't match that of the " & parent_component
+        "Dest length of protocol checker doesn't match that of the " & parent_component
       );
       check_equal(
         axi_stream_checker,
         protocol_checker.p_user_length,
         user_length,
-        "User length of monitor doesn't match that of the " & parent_component
+        "User length of protocol checker doesn't match that of the " & parent_component
       );
       return protocol_checker;
     end if;
@@ -495,7 +495,7 @@ package body axi_stream_pkg is
   begin
     -- Since values are in the 0 - 1 range, we can have the full resolution of the mantissa fit within
     -- an integer if reals are implemented as single-precision floats.
-    set(result, 0, integer(stall_config.stall_probability * (2.0 ** 23)));
+    set(result, 0, integer(stall_config.stall_probability * (2.0 ** single_precision_mantissa_length)));
     set(result, 1, stall_config.min_stall_cycles);
     set(result, 2, stall_config.max_stall_cycles);
 
@@ -522,7 +522,7 @@ package body axi_stream_pkg is
     inactive_policy : inactive_axi_stream_policy_t
   ) is
   begin
-    set(master.p_config, p_interactive_policy_idx, to_integer(to_integer_vector_ptr(inactive_policy)));
+    set(master.p_config, p_inactive_policy_idx, to_integer(to_integer_vector_ptr(inactive_policy)));
   end;
 
   impure function new_axi_stream_master(
@@ -558,7 +558,7 @@ package body axi_stream_pkg is
       p_logger           => logger,
       p_monitor          => p_monitor,
       p_protocol_checker => p_protocol_checker,
-      p_config           => new_integer_vector_ptr(p_interactive_policy_idx + 1)
+      p_config           => new_integer_vector_ptr(p_inactive_policy_idx + 1)
     );
 
     set_stall_config(handle, stall_config);
@@ -998,7 +998,7 @@ package body axi_stream_pkg is
   impure function p_to_stall_config(vec : integer_vector_ptr_t) return stall_config_t is
     variable stall_config : stall_config_t;
   begin
-    stall_config.stall_probability := real(get(vec, 0)) * (2.0 ** (-23));
+    stall_config.stall_probability := real(get(vec, 0)) * (2.0 ** (-single_precision_mantissa_length));
     stall_config.min_stall_cycles := get(vec, 1);
     stall_config.max_stall_cycles := get(vec, 2);
 
@@ -1102,15 +1102,4 @@ package body axi_stream_pkg is
     return stall_config;
   end;
 
-  function is_u(value : std_ulogic_vector) return boolean is
-  begin
-    for idx in value'range loop
-      if value(idx) /= 'U' then
-        return false;
-      end if;
-    end loop;
-
-    return true;
-  end;
-
 end package body;

vunit/vhdl/verification_components/src/axi_stream_private_pkg.vhd

@@ -31,6 +31,11 @@ package axi_stream_private_pkg is
 
   impure function get_stall_config(master : axi_stream_master_t) return stall_config_t;
   impure function get_stall_config(slave : axi_stream_slave_t) return stall_config_t;
+
+  function resolve_tstrb(
+    tkeep : std_logic_vector;
+    tstrb : std_logic_vector
+  ) return std_logic_vector;
 end package;
 
 package body axi_stream_private_pkg is
@@ -62,7 +67,7 @@ package body axi_stream_private_pkg is
 
     for sig in start to stop loop
       set(
-        to_integer_vector_ptr(get(master.p_config, p_interactive_policy_idx)),
+        to_integer_vector_ptr(get(master.p_config, p_inactive_policy_idx)),
         axi_stream_signal_t'pos(sig),
         inactive_bus_policy_t'pos(inactive_policy)
       );
@@ -81,7 +86,7 @@ package body axi_stream_private_pkg is
 
   impure function get_inactive_axi_stream_policy(master : axi_stream_master_t) return inactive_axi_stream_policy_t is
   begin
-    return to_inactive_axi_stream_policy(to_integer_vector_ptr(get(master.p_config, p_interactive_policy_idx)));
+    return to_inactive_axi_stream_policy(to_integer_vector_ptr(get(master.p_config, p_inactive_policy_idx)));
   end;
 
   impure function get_stall_config(master : axi_stream_master_t) return stall_config_t is
@@ -93,4 +98,16 @@ package body axi_stream_private_pkg is
   begin
     return p_to_stall_config(to_integer_vector_ptr(get(slave.p_config, p_stall_config_idx)));
   end;
+
+  function resolve_tstrb(
+    tkeep : std_logic_vector;
+    tstrb : std_logic_vector
+  ) return std_logic_vector is
+  begin
+    if tstrb = (tstrb'range => 'U') then
+      return tkeep;
+    else
+      return tstrb;
+    end if;
+  end;
 end package body;

vunit/vhdl/verification_components/src/axi_stream_protocol_checker.vhd

@@ -11,6 +11,7 @@ use ieee.numeric_std_unsigned.all;
 use std.textio.all;
 
 use work.axi_stream_pkg.all;
+use work.axi_stream_private_pkg.all;
 use work.check_pkg.all;
 use work.checker_pkg.all;
 use work.event_common_pkg.is_active;
@@ -91,7 +92,7 @@ architecture a of axi_stream_protocol_checker is
     return ret;
   end function;
 begin
-  tstrb_resolved <= tkeep when is_u(tstrb) else tstrb;
+  tstrb_resolved <= resolve_tstrb(tkeep, tstrb);
   handshake_is_not_x <= '1' when not is_x(tvalid) and not is_x(tready) else '0';
 
   -- AXI4STREAM_ERRM_TDATA_STABLE TDATA remains stable when TVALID is asserted,

vunit/vhdl/verification_components/src/axi_stream_slave.vhd

@@ -82,14 +82,6 @@ begin
   end process;
 
   bus_process : process
-    procedure probability_stall_axi_stream(
-      signal aclk : in std_logic;
-      axi_stream  : in axi_stream_slave_t;
-      rnd         : inout RandomPType) is
-    begin
-      probability_stall_axi_stream(aclk, get_stall_config(axi_stream), rnd);
-    end procedure;
-
     procedure check_field(got, exp : std_logic_vector; msg : string) is
     begin
       if got'length /= 0 and exp'length /= 0 then
@@ -135,13 +127,13 @@ begin
         elsif msg_type = stream_pop_msg or msg_type = pop_axi_stream_msg or msg_type = check_axi_stream_msg then
 
           -- stall according to probability configuration
-          probability_stall_axi_stream(aclk, slave, rnd);
+          probability_stall_axi_stream(aclk, get_stall_config(slave), rnd);
 
           tready <= '1';
           wait until (tvalid and tready) = '1' and rising_edge(aclk);
           tready <= '0';
 
-          tstrb_resolved := tkeep when is_u(tstrb) else tstrb;
+          tstrb_resolved := resolve_tstrb(tkeep, tstrb);
           if msg_type = stream_pop_msg or msg_type = pop_axi_stream_msg then
             axi_stream_transaction := (
               tdata => tdata,