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cypress_pd_common.c
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2562 lines (2193 loc) · 70.2 KB
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/* Copyright 2022 The ChromiumOS Authors
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
#include <atomic.h>
#include <zephyr/init.h>
#include "gpio/gpio_int.h"
#include "battery.h"
#include "board_function.h"
#include "charge_manager.h"
#include "charge_state.h"
#include "console.h"
#include "cypress_pd_common.h"
#include "common_cpu_power.h"
#include "driver/charger/isl9241.h"
#include "extpower.h"
#include "gpio.h"
#include "hooks.h"
#include "i2c.h"
#include "power.h"
#include "task.h"
#include "ucsi.h"
#include "usb_pd.h"
#include "usb_pd_tcpm.h"
#include "usb_emsg.h"
#include "usb_tc_sm.h"
#include "util.h"
#include "throttle_ap.h"
#include "zephyr_console_shim.h"
#ifdef CONFIG_BOARD_LOTUS
#include "gpu.h"
#include "cpu_power.h"
#include "board_charger.h"
#endif
#define CPRINTS(format, args...) cprints(CC_USBCHARGE, format, ##args)
#define CPRINTF(format, args...) cprintf(CC_USBCHARGE, format, ##args)
#define PRODUCT_ID 0x0001
#define VENDOR_ID 0x32ac
/*
* Unimplemented functions:
* 1. Control port current 3A/1.5A for GRL test.
* 2. Control port VBUS enable/disable.
* 3. Update system power state to PD chip. (Avoid PD chip does the error recovery)
* 4. Control PD chip compliance mode
* 5. Flash PD flow
* 6. Extended message handler
* 7. UCSI handler
*/
static struct pd_chip_config_t pd_chip_config[] = {
[PD_CHIP_0] = {
.i2c_port = I2C_PORT_PD_MCU0,
.addr_flags = CCG_I2C_CHIP0 | I2C_FLAG_ADDR16_LITTLE_ENDIAN,
.state = CCG_STATE_POWER_ON,
.gpio = GPIO_EC_PD_INTA_L,
},
[PD_CHIP_1] = {
.i2c_port = I2C_PORT_PD_MCU1,
.addr_flags = CCG_I2C_CHIP1 | I2C_FLAG_ADDR16_LITTLE_ENDIAN,
.state = CCG_STATE_POWER_ON,
.gpio = GPIO_EC_PD_INTB_L,
},
};
BUILD_ASSERT(ARRAY_SIZE(pd_chip_config) == PD_CHIP_COUNT);
static struct pd_port_current_state_t pd_port_states[] = {
[PD_PORT_0] = {
},
[PD_PORT_1] = {
},
[PD_PORT_2] = {
},
[PD_PORT_3] = {
}
};
struct extended_msg rx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
struct extended_msg tx_emsg[CONFIG_USB_PD_PORT_MAX_COUNT];
static int prev_charge_port = -1;
static uint8_t pd_c_fet_active_port;
static bool verbose_msg_logging;
static bool firmware_update;
static uint8_t pd_epr_in_progress;
/*****************************************************************************/
/* Internal functions */
static void cypd_update_port_state(int controller, int port);
static void cypd_pdo_reset_deferred(void);
static void cypd_set_prepare_pdo(int controller, int port);
int cypd_write_reg_block(int controller, int reg, void *data, int len)
{
int rv;
uint16_t i2c_port = pd_chip_config[controller].i2c_port;
uint16_t addr_flags = pd_chip_config[controller].addr_flags;
rv = i2c_write_offset16_block(i2c_port, addr_flags, reg, data, len);
if (rv != EC_SUCCESS)
CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
return rv;
}
static int cypd_write_reg16(int controller, int reg, int data)
{
int rv;
uint16_t i2c_port = pd_chip_config[controller].i2c_port;
uint16_t addr_flags = pd_chip_config[controller].addr_flags;
rv = i2c_write_offset16(i2c_port, addr_flags, reg, data, 2);
if (rv != EC_SUCCESS)
CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
return rv;
}
int cypd_write_reg8(int controller, int reg, int data)
{
int rv;
uint16_t i2c_port = pd_chip_config[controller].i2c_port;
uint16_t addr_flags = pd_chip_config[controller].addr_flags;
rv = i2c_write_offset16(i2c_port, addr_flags, reg, data, 1);
if (rv != EC_SUCCESS)
CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
return rv;
}
int cypd_read_reg_block(int controller, int reg, void *data, int len)
{
int rv;
uint16_t i2c_port = pd_chip_config[controller].i2c_port;
uint16_t addr_flags = pd_chip_config[controller].addr_flags;
rv = i2c_read_offset16_block(i2c_port, addr_flags, reg, data, len);
if (rv != EC_SUCCESS)
CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
return rv;
}
static int cypd_read_reg16(int controller, int reg, int *data)
{
int rv;
uint16_t i2c_port = pd_chip_config[controller].i2c_port;
uint16_t addr_flags = pd_chip_config[controller].addr_flags;
rv = i2c_read_offset16(i2c_port, addr_flags, reg, data, 2);
if (rv != EC_SUCCESS)
CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
return rv;
}
static int cypd_read_reg8(int controller, int reg, int *data)
{
int rv;
uint16_t i2c_port = pd_chip_config[controller].i2c_port;
uint16_t addr_flags = pd_chip_config[controller].addr_flags;
rv = i2c_read_offset16(i2c_port, addr_flags, reg, data, 1);
if (rv != EC_SUCCESS)
CPRINTS("%s failed: ctrl=0x%x, reg=0x%02x", __func__, controller, reg);
return rv;
}
static int cypd_reset(int controller)
{
/*
* Device Reset: This command is used to request the CCG device to perform a soft reset
* and start at the boot-loader stage again
* Note: need barrel AC or battery
*/
return cypd_write_reg16(controller, CCG_RESET_REG, CCG_RESET_CMD);
}
int cypd_get_int(int controller, int *intreg)
{
int rv;
rv = cypd_read_reg8(controller, CCG_INTR_REG, intreg);
if (rv != EC_SUCCESS)
CPRINTS("%s failed: ctrl=0x%x, rv=0x%02x", __func__, controller, rv);
return rv;
}
int cypd_clear_int(int controller, int mask)
{
int rv;
rv = cypd_write_reg8(controller, CCG_INTR_REG, mask);
if (rv != EC_SUCCESS)
CPRINTS("%s failed: ctrl=0x%x, mask=0x%02x", __func__, controller, mask);
return rv;
}
int cypd_wait_for_ack(int controller, int timeout_ms)
{
const struct gpio_dt_spec *intr = gpio_get_dt_spec(pd_chip_config[controller].gpio);
timestamp_t start = get_time();
/* wait for interrupt ack to be asserted */
do {
if (gpio_pin_get_dt(intr) == 0)
break;
usleep(100);
} while (time_since32(start) < (timeout_ms * MSEC));
/* make sure response is ok */
if (gpio_pin_get_dt(intr) != 0) {
CPRINTS("%s timeout on interrupt", __func__);
return EC_ERROR_INVAL;
}
return EC_SUCCESS;
}
static int cypd_write_reg8_wait_ack(int controller, int reg, int data)
{
int rv = EC_SUCCESS;
int intr_status;
int event;
int cmd_port = -1;
int ack_mask = 0;
int expected_ack_mask = 0;
const struct gpio_dt_spec *intr = gpio_get_dt_spec(pd_chip_config[controller].gpio);
if (reg < 0x1000) {
expected_ack_mask = CCG_DEV_INTR;
cmd_port = -1;
} else if (reg < 0x2000) {
expected_ack_mask = CCG_PORT0_INTR;
cmd_port = 0;
} else {
expected_ack_mask = CCG_PORT1_INTR;
cmd_port = 1;
}
if (gpio_pin_get_dt(intr) == 0) {
/* we may have a pending interrupt */
rv = cypd_get_int(controller, &intr_status);
CPRINTS("%s pre 0x%x ", __func__, intr_status);
if (intr_status & CCG_DEV_INTR) {
rv = cypd_read_reg16(controller, CCG_RESPONSE_REG, &event);
if (event < 0x80) {
cypd_clear_int(controller, CCG_DEV_INTR);
}
usleep(50);
}
}
rv = cypd_write_reg8(controller, reg, data);
if (rv != EC_SUCCESS)
CPRINTS("Write Reg8 0x%x fail!", reg);
if (cypd_wait_for_ack(controller, 100) != EC_SUCCESS) {
CPRINTS("%s timeout on interrupt", __func__);
return EC_ERROR_INVAL;
}
rv = cypd_get_int(controller, &intr_status);
if (rv != EC_SUCCESS)
CPRINTS("Get INT Fail");
if (intr_status & CCG_DEV_INTR && cmd_port == -1) {
rv = cypd_read_reg16(controller, CCG_RESPONSE_REG, &event);
if (rv != EC_SUCCESS)
CPRINTS("fail to read DEV response");
ack_mask = CCG_DEV_INTR;
} else if (intr_status & CCG_PORT0_INTR && cmd_port == 0) {
rv = cypd_read_reg16(controller, CCG_PORT_PD_RESPONSE_REG(0), &event);
if (rv != EC_SUCCESS)
CPRINTS("fail to read P0 response");
ack_mask = CCG_PORT0_INTR;
} else if (intr_status & CCG_PORT1_INTR && cmd_port == 1) {
rv = cypd_read_reg16(controller, CCG_PORT_PD_RESPONSE_REG(1), &event);
if (rv != EC_SUCCESS)
CPRINTS("fail to read P1 response");
ack_mask = CCG_PORT1_INTR;
} else {
CPRINTS("%s C:%d Unexpected response 0x%x to reg 0x%x",
__func__, controller, intr_status, reg);
rv = cypd_read_reg16(controller, CCG_RESPONSE_REG, &event);
CPRINTS("Dev 0x%x", event);
rv = cypd_read_reg16(controller, CCG_PORT_PD_RESPONSE_REG(0), &event);
CPRINTS("P0 0x%x", event);
rv = cypd_read_reg16(controller, CCG_PORT_PD_RESPONSE_REG(1), &event);
CPRINTS("P1 0x%x", event);
}
/* only clear response code let main task handle event code */
if (event < 0x80) {
cypd_clear_int(controller, ack_mask);
if (event != CCG_RESPONSE_SUCCESS) {
CPRINTS("%s C:%d 0x%x response 0x%x",
__func__, controller, reg, event);
}
rv = (event == CCG_RESPONSE_SUCCESS) ? EC_SUCCESS : EC_ERROR_INVAL;
}
usleep(50);
return rv;
}
void cypd_print_buff(const char *msg, void *buff, int len)
{
int i;
uint8_t *data = (uint8_t *)buff;
CPRINTF("%s 0x", msg);
for (i = len-1; i >= 0; i--) {
CPRINTF("%02x", data[i]);
}
CPRINTF("\n");
}
#ifdef CONFIG_BOARD_LOTUS
static void update_external_cc_mux(int port, int cc)
{
if (port == 1) {
switch(cc) {
case POLARITY_CC1:
gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc1), 1);
gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc2), 0);
break;
case POLARITY_CC2:
gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc1), 0);
gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc2), 1);
break;
default:
gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc1), 0);
gpio_pin_set_dt(GPIO_DT_FROM_NODELABEL(gpio_usb3_ec_p2_cc2), 0);
}
}
}
#define EXIT_EPR BIT(4)
#define ENTER_EPR BIT(5)
#define EPR_PROCESS_MASK (EXIT_EPR + ENTER_EPR)
static void epr_flow_pending_deferred(void)
{
int port_idx;
/**
* Sometimes, EC does not receive the EPR event/NOT support event from PD chip.
* Retry the last action.
*/
for (port_idx = 0; port_idx < PD_PORT_COUNT; port_idx++) {
if (pd_epr_in_progress & BIT(port_idx)) {
if (pd_port_states[port_idx].epr_retry_count > 4) {
/* restore the input current limit if we retry 4 times */
pd_port_states[port_idx].epr_retry_count = 0;
pd_port_states[port_idx].epr_support = 0;
pd_epr_in_progress &= EPR_PROCESS_MASK;
if (prev_charge_port != -1)
cypd_update_port_state((prev_charge_port & 0x02) >> 1,
prev_charge_port & BIT(0));
}
/**
* There is a low risk situation.
* If both the EXIT EPR and ENTER EPR flags are set simultaneously,
* it will cause epr_retry_count to be incremented twice.
*/
if (pd_epr_in_progress & EXIT_EPR) {
CPRINTS("C%d exit EPR stuck, retry!", port_idx);
exit_epr_mode();
pd_port_states[port_idx].epr_retry_count++;
}
if (pd_epr_in_progress & ENTER_EPR) {
CPRINTS("C%d enter EPR stuck, retry!", port_idx);
enter_epr_mode();
pd_port_states[port_idx].epr_retry_count++;
}
} else
pd_port_states[port_idx].epr_retry_count = 0;
}
}
DECLARE_DEFERRED(epr_flow_pending_deferred);
void enter_epr_mode(void)
{
int port_idx;
/**
* Only enter EPR mode when the system in S0 state.
* 1. Resume from S0i3 mode
* 2. Power up from S5/G3 state (after error recovery, will enter EPR mode automatically)
* 3. battery in normal mode
*/
if (chipset_in_state(CHIPSET_STATE_ANY_OFF) ||
battery_is_cut_off() || battery_cutoff_in_progress())
return;
/**
* PD negotiation completed and in Sink Role,
* execute the CCG command to enter the EPR mode
*/
for (port_idx = 0; port_idx < PD_PORT_COUNT; port_idx++) {
if ((pd_port_states[port_idx].pd_state) &&
(pd_port_states[port_idx].power_role == PD_ROLE_SINK) &&
(pd_port_states[port_idx].epr_active == 0) &&
(pd_port_states[port_idx].epr_support == 1)) {
/* BIT(4): epr in progress, BIT(1) - BIT(3) which port */
pd_epr_in_progress |= (BIT(port_idx) + ENTER_EPR);
/* avoid the pmf is higher when the system resume from S0ix */
update_pmf_events(BIT(PD_PROGRESS_ENTER_EPR_MODE),
!!(pd_epr_in_progress & ~EPR_PROCESS_MASK));
if (battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED) {
/* Enable learn mode to discharge on AC */
board_discharge_on_ac(1);
/* Set input current to 0mA */
charger_set_input_current_limit(0, 0);
}
cypd_write_reg8((port_idx & 0x2) >> 1,
CCG_PD_CONTROL_REG(port_idx & 0x1),
CCG_PD_CMD_INITIATE_EPR_ENTRY);
hook_call_deferred(&epr_flow_pending_deferred_data, 200 * MSEC);
}
}
}
DECLARE_DEFERRED(enter_epr_mode);
void enter_epr_mode_without_battery(void)
{
if ((battery_get_disconnect_state() == BATTERY_DISCONNECTED) ||
(battery_is_present() != BP_YES))
enter_epr_mode();
}
DECLARE_HOOK(HOOK_CHIPSET_STARTUP, enter_epr_mode_without_battery, HOOK_PRIO_DEFAULT);
void exit_epr_mode(void)
{
int port_idx;
for (port_idx = 0; port_idx < PD_PORT_COUNT; port_idx++) {
if (pd_port_states[port_idx].epr_active == 1) {
/* BIT(4): epr in progress, BIT(1) - BIT(3) which port */
pd_epr_in_progress |= (BIT(port_idx) + EXIT_EPR);
/* do not set learn mode when battery is cut off */
if (!battery_cutoff_in_progress() && !battery_is_cut_off() &&
(battery_get_disconnect_state() == BATTERY_NOT_DISCONNECTED)) {
/* Enable learn mode to discharge on AC */
board_discharge_on_ac(1);
/* Set input current to 0mA */
charger_set_input_current_limit(0, 0);
} else {
update_pmf_events(BIT(PD_PROGRESS_EXIT_EPR_MODE),
!!(pd_epr_in_progress & ~EPR_PROCESS_MASK));
}
cypd_write_reg8((port_idx & 0x2) >> 1,
CCG_PD_CONTROL_REG(port_idx & 0x1),
CCG_PD_CMD_INITIATE_EPR_EXIT);
hook_call_deferred(&epr_flow_pending_deferred_data, 1000 * MSEC);
}
}
}
DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, exit_epr_mode, HOOK_PRIO_FIRST);
#endif
static void pd0_update_state_deferred(void)
{
task_set_event(TASK_ID_CYPD, CCG_EVT_STATE_CTRL_0);
}
DECLARE_DEFERRED(pd0_update_state_deferred);
static void pd1_update_state_deferred(void)
{
task_set_event(TASK_ID_CYPD, CCG_EVT_STATE_CTRL_1);
}
DECLARE_DEFERRED(pd1_update_state_deferred);
static void update_power_state_deferred(void)
{
task_set_event(TASK_ID_CYPD, CCG_EVT_UPDATE_PWRSTAT);
}
DECLARE_DEFERRED(update_power_state_deferred);
static void cypd_enable_interrupt(int controller, int enable_ndisable)
{
if (controller) {
if (enable_ndisable)
gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip1_interrupt));
else
gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip1_interrupt));
}else {
if (enable_ndisable)
gpio_enable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip0_interrupt));
else
gpio_disable_dt_interrupt(GPIO_INT_FROM_NODELABEL(int_pd_chip0_interrupt));
}
}
static void cypd_print_version(int controller, const char *vtype, uint8_t *data)
{
/*
* Base version: Cypress release version
* Application version: FAE release version
*/
CPRINTS("Controller %d %s version B:%X.%X.%X.%X , AP:%X.%X.%X",
controller, vtype,
(data[3]>>4) & 0xF, (data[3]) & 0xF, data[2], data[0] + (data[1]<<8),
(data[7]>>4) & 0xF, (data[7]) & 0xF, data[6]);
}
static void cypd_get_version(int controller)
{
int rv;
int i;
uint8_t data[24];
uint16_t i2c_port = pd_chip_config[controller].i2c_port;
uint16_t addr_flags = pd_chip_config[controller].addr_flags;
rv = i2c_read_offset16_block(i2c_port, addr_flags, CCG_READ_ALL_VERSION_REG, data, 24);
if (rv != EC_SUCCESS)
CPRINTS("READ_ALL_VERSION_REG failed");
cypd_print_version(controller, "App1", data+8);
cypd_print_version(controller, "App2", data+16);
/* store the FW2 version into pd_chip_info struct */
for (i = 0; i < 8; i++)
pd_chip_config[controller].version[i] = data[16+i];
}
static void pdo_init_deferred(void)
{
task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_INIT_0);
}
DECLARE_DEFERRED(pdo_init_deferred);
static void cypd_pdo_init(int controller, int port, uint8_t profile)
{
int rv;
/*
* EC needs to provide the data for all Source PDOs when doing a dynamic update of the PDOs.
* If less than 7 PDOs are required, the remaining PDO values should be set to 0.
*/
uint8_t pdos_reg[32] = {
0x50, 0x43, 0x52, 0x53, /* “SRCP” */
0x96, 0x90, 0x01, 0x27, /* PDO0 - 1.5A */
0x2c, 0x91, 0x01, 0x27, /* PDO1 - 3A */
0x00, 0x00, 0x00, 0x00, /* PDO2 */
0x00, 0x00, 0x00, 0x00, /* PDO3 */
0x00, 0x00, 0x00, 0x00, /* PDO4 */
0x00, 0x00, 0x00, 0x00, /* PDO5 */
0x00, 0x00, 0x00, 0x00 /* PDO6 */
};
rv = cypd_write_reg_block(controller, CCG_WRITE_DATA_MEMORY_REG(port, 0),
pdos_reg, sizeof(pdos_reg));
if (rv != EC_SUCCESS)
CPRINTS("SET CCG_MEMORY failed");
rv = cypd_write_reg8_wait_ack(controller, CCG_SELECT_SOURCE_PDO_REG(port), profile);
if (rv != EC_SUCCESS)
CPRINTS("SET CCG_SELECT_REG failed");
memset(pdos_reg, 0, sizeof(pdos_reg));
/* Clear Signature “SRCP” for PDO update finish */
rv = cypd_write_reg_block(controller, CCG_WRITE_DATA_MEMORY_REG(port, 0),
pdos_reg, sizeof(pdos_reg));
if (rv != EC_SUCCESS)
CPRINTS("CLEAR CCG_MEMORY failed");
}
static int cypd_select_rp(int port, uint8_t profile)
{
int rv;
CPRINTF("P:%d SET TYPEC RP=%d", port, profile);
rv = cypd_write_reg8_wait_ack(PORT_TO_CONTROLLER(port),
CCG_PD_CONTROL_REG(PORT_TO_CONTROLLER_PORT(port)),
profile);
if (rv != EC_SUCCESS)
CPRINTS("SET TYPEC RP failed");
return rv;
}
static int cypd_select_pdo(int controller, int port, uint8_t profile)
{
int rv;
rv = cypd_write_reg8_wait_ack(controller, CCG_SELECT_SOURCE_PDO_REG(port), profile);
if (rv != EC_SUCCESS)
CPRINTS("SET CCG_SELECT_REG failed");
return rv;
}
static int pd_3a_flag;
static int pd_3a_set;
static int pd_3a_controller;
static int pd_3a_port;
static int pd_ports_1_5A_flag[PD_PORT_COUNT];
int cypd_port_3a_status(int controller, int port)
{
int port_idx = (controller << 1) + port;
if (pd_3a_flag &&
controller == pd_3a_controller &&
port_idx == pd_3a_port)
return true;
return false;
}
int cypd_port_3a_set(int controller, int port)
{
int port_idx = (controller << 1) + port;
if (pd_3a_set)
return false;
pd_3a_set = 1;
pd_3a_flag = 1;
pd_3a_controller = controller;
pd_3a_port = port_idx;
return true;
}
void cypd_port_1_5a_set(int controller, int port)
{
int port_idx = (controller << 1) + port;
pd_ports_1_5A_flag[port_idx] = 1;
}
int cypd_port_force_3A(int controller, int port)
{
int port_idx = (controller << 1) + port;
int port_1_5A_idx = 0;
int i;
for (i = 0; i < PD_PORT_COUNT; i++) {
port_1_5A_idx += pd_ports_1_5A_flag[i];
}
if (port_1_5A_idx >= 3) {
if (!pd_ports_1_5A_flag[port_idx])
return true;
}
return false;
}
void cypd_release_port(int controller, int port)
{
int port_idx = (controller << 1) + port;
/* if port disconnect should set RP and PDO to default */
cypd_select_rp(port_idx, CCG_PD_CMD_SET_TYPEC_1_5A);
cypd_select_pdo(controller, port, CCG_PD_CMD_SET_TYPEC_3A);
if (cypd_port_3a_status(controller, port)) {
pd_3a_set = 0;
pd_3a_flag = 0;
}
pd_ports_1_5A_flag[port_idx] = 0;
}
void cypd_clear_port(int controller, int port)
{
int port_idx = (controller << 1) + port;
if (cypd_port_3a_status(controller, port)) {
pd_3a_set = 0;
pd_3a_flag = 0;
}
pd_ports_1_5A_flag[port_idx] = 0;
}
/*
* function for profile check, if profile not change
* don't send again.
*/
int cypd_profile_check(int controller, int port)
{
int port_idx = (controller << 1) + port;
return pd_ports_1_5A_flag[port_idx] != 0;
}
static void pdo_c0p0_deferred(void)
{
task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_C0P0);
}
DECLARE_DEFERRED(pdo_c0p0_deferred);
static void pdo_c0p1_deferred(void)
{
task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_C0P1);
}
DECLARE_DEFERRED(pdo_c0p1_deferred);
static void pdo_c1p0_deferred(void)
{
task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_C1P0);
}
DECLARE_DEFERRED(pdo_c1p0_deferred);
static void pdo_c1p1_deferred(void)
{
task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_C1P1);
}
DECLARE_DEFERRED(pdo_c1p1_deferred);
static void cypd_set_prepare_pdo(int controller, int port)
{
switch (controller) {
case 0:
if (!port)
hook_call_deferred(&pdo_c0p0_deferred_data, 2000 * MSEC);
else
hook_call_deferred(&pdo_c0p1_deferred_data, 2100 * MSEC);
break;
case 1:
if (!port)
hook_call_deferred(&pdo_c1p0_deferred_data, 2000 * MSEC);
else
hook_call_deferred(&pdo_c1p1_deferred_data, 2100 * MSEC);
break;
}
}
static int cypd_modify_profile(int controller, int port, int profile)
{
int rv;
int port_idx = (controller << 1) + port;
if (verbose_msg_logging)
CPRINTS("PD Select PDO %s ", profile & 0x02 ? "3A" : "1.5A");
if (profile == CCG_PD_CMD_SET_TYPEC_3A) {
rv = cypd_select_rp(port_idx, profile);
if (rv != EC_SUCCESS)
return rv;
}
rv = cypd_select_pdo(controller, port, profile);
if (rv != EC_SUCCESS) {
CPRINTS("PD Select PDO %s failed", profile & 0x02 ? "3A" : "1.5A");
cypd_clear_port(controller, port);
cypd_set_prepare_pdo(controller, port);
return rv;
}
/* Lock 1.5A port */
if (profile == CCG_PD_CMD_SET_TYPEC_1_5A)
cypd_port_1_5a_set(controller, port);
return EC_SUCCESS;
}
int cypd_modify_safety_power_1_5A(int controller, int port)
{
int rv;
int port_idx = (controller << 1) + port;
if (verbose_msg_logging)
CPRINTS("Safety level trigger force PDO 1.5A");
rv = cypd_select_rp(port_idx, CCG_PD_CMD_SET_TYPEC_1_5A);
rv = cypd_select_pdo(controller, port, CCG_PD_CMD_SET_TYPEC_1_5A);
if (rv != EC_SUCCESS) {
cypd_clear_port(controller, port);
cypd_set_prepare_pdo(controller, port);
return rv;
}
pd_3a_set = 0;
pd_3a_flag = 0;
pd_ports_1_5A_flag[port_idx] = 1;
return EC_SUCCESS;
}
void cypd_set_typec_profile(int controller, int port)
{
int rv;
uint8_t pd_status_reg[4];
uint8_t rdo_reg[4];
int rdo_max_current = 0;
int port_idx = (controller << 1) + port;
rv = cypd_read_reg_block(controller, CCG_PD_STATUS_REG(port), pd_status_reg, 4);
if (rv != EC_SUCCESS)
CPRINTS("CYP5525_PD_STATUS_REG failed");
/*do we have a valid PD contract*/
pd_port_states[port_idx].pd_state = pd_status_reg[1] & BIT(2) ? 1 : 0;
pd_port_states[port_idx].power_role =
pd_status_reg[1] & BIT(0) ? PD_ROLE_SOURCE : PD_ROLE_SINK;
if (pd_port_states[port_idx].power_role == PD_ROLE_SOURCE) {
if (pd_port_states[port_idx].pd_state) {
#ifdef CONFIG_BOARD_LOTUS
/*
* If safety level(LEVEL_TYPEC_1_5A) is triggered,
* force 1.5A pdo to device.
*/
if (safety_force_typec_1_5A()) {
rv = cypd_modify_profile(controller, port,
CCG_PD_CMD_SET_TYPEC_1_5A);
return;
}
#endif
/*
* first time set 3A PDO to device
* when device request RDO <= 1.5A
* resend 1.5A pdo to device
*/
cypd_read_reg_block(controller, CCG_CURRENT_RDO_REG(port), rdo_reg, 4);
rdo_max_current = (((rdo_reg[1]>>2) + (rdo_reg[2]<<6)) & 0x3FF)*10;
if ((cypd_port_force_3A(controller, port) && !pd_3a_flag) ||
cypd_port_3a_status(controller, port)) {
if (!cypd_port_3a_set(controller, port))
return;
rv = cypd_modify_profile(controller, port,
CCG_PD_CMD_SET_TYPEC_3A);
} else if (rdo_max_current <= 1500) {
if (cypd_profile_check(controller, port))
return;
rv = cypd_modify_profile(controller, port,
CCG_PD_CMD_SET_TYPEC_1_5A);
} else if (!pd_3a_flag && cypd_port_3a_set(controller, port))
rv = cypd_modify_profile(controller, port,
CCG_PD_CMD_SET_TYPEC_3A);
else if (!cypd_profile_check(controller, port))
rv = cypd_modify_profile(controller, port,
CCG_PD_CMD_SET_TYPEC_1_5A);
} else {
cypd_write_reg8(controller, CCG_PD_CONTROL_REG(port),
CCG_PD_CMD_SET_TYPEC_1_5A);
}
}
cypd_update_port_state(controller, port);
}
void cypd_port_current_setting(void)
{
for (int i = 0; i < PD_CHIP_COUNT; i++) {
cypd_set_prepare_pdo(i, 0);
cypd_set_prepare_pdo(i, 1);
}
}
static void cypd_pdo_reset_deferred(void)
{
task_set_event(TASK_ID_CYPD, CCG_EVT_PDO_RESET);
}
DECLARE_DEFERRED(cypd_pdo_reset_deferred);
static void cypd_ppm_port_clear(void)
{
memset(pd_ports_1_5A_flag, 0, sizeof(pd_ports_1_5A_flag));
pd_3a_set = 0;
/* need init PDO again because PD chip will clear PDO data */
hook_call_deferred(&pdo_init_deferred_data, 1);
}
/*
* send a message using DM_CONTROL to port partner
* pd_header is using chromium PD header with upper bits defining SOP type
* pd30 is set for batttery status messages
* response timer is set to false for messages that are a response
* data includes
* pd header bytes 0 -1
* message, or extmessage header - then data
* length should include length of all data after pd header
*/
void cypd_send_msg(int controller, int port, uint32_t pd_header, uint16_t ext_hdr,
bool pd30, bool response_timer, void *data, uint32_t data_size)
{
uint16_t header[2] = {0};
uint16_t dm_control_data;
/**
* The extended message data should be written to the write data memory
* in the following format:
* Byte 0 : Message type [4:0]
* Byte 1 : Reserved
* Byte 3 - 2 : Extended message header
* Byte N - 4 : data
*/
header[0] = pd_header;
header[1] = ext_hdr;
cypd_write_reg_block(controller, CCG_WRITE_DATA_MEMORY_REG(port, 0),
(void *)header, 4);
cypd_write_reg_block(controller, CCG_WRITE_DATA_MEMORY_REG(port, 4),
data, data_size);
/**
* The DM_CONTROL register should then be written to in the following format:
* Byte 0
* - BIT 1 - 0 : Packet type should be set to SOP(0), SOP'(1), or SOP''(2).
* - BIT 2 : PD 3.0 Message bit (Bit 2) should be clear.
* - BIT 3 : Extended message bit (Bit 3) should be set.
* - BIT 4 : Respoonse timer disable bit should be set as desired.
* Byte 1 : The data length specified here will be the actual length of data
* written into the write data memory, inclusive of the 4 byte header
*
* TODO: Need to process chunk extended message [4:32]
*/
dm_control_data = PD_HEADER_GET_SOP(pd_header);
if (ext_hdr)
dm_control_data |= CCG_DM_CTRL_EXTENDED_DATA_REQUEST;
if (pd30)
dm_control_data |= CCG_DM_CTRL_PD3_DATA_REQUEST;
if (!response_timer)
dm_control_data |= CCG_DM_CTRL_SENDER_RESPONSE_TIMER_DISABLE;
dm_control_data += ((data_size + 4) << 8);
cypd_write_reg16(controller, CCG_DM_CONTROL_REG(port), dm_control_data);
}
void cypd_response_get_battery_capability(int controller, int port,
uint32_t pd_header, enum tcpci_msg_type sop_type)
{
int port_idx = (controller << 1) + port;
int ext_header = 0;
bool chunked = PD_EXT_HEADER_CHUNKED(rx_emsg[port_idx].header);
uint16_t msg[5] = {0, 0, 0, 0, 0};
uint32_t header = PD_EXT_BATTERY_CAP + PD_HEADER_SOP(sop_type);
ext_header = 9;
/* Set extended header */
if (chunked) {
ext_header |= BIT(15);
}
/* Set VID */
msg[0] = VENDOR_ID;
/* Set PID */
msg[1] = PRODUCT_ID;
if (battery_is_present() == BP_YES) {
/*
* We only have one fixed battery,
* so make sure batt cap ref is 0.
*/
if (rx_emsg[port_idx].buf[0] != 0) {
/* Invalid battery reference */
msg[4] = 1;
} else {
uint32_t v;
uint32_t c;
/*
* The Battery Design Capacity field shall return the
* Battery’s design capacity in tenths of Wh. If the
* Battery is Hot Swappable and is not present, the
* Battery Design Capacity field shall be set to 0. If
* the Battery is unable to report its Design Capacity,
* it shall return 0xFFFF
*/
msg[2] = 0xffff;
/*
* The Battery Last Full Charge Capacity field shall
* return the Battery’s last full charge capacity in
* tenths of Wh. If the Battery is Hot Swappable and
* is not present, the Battery Last Full Charge Capacity
* field shall be set to 0. If the Battery is unable to
* report its Design Capacity, the Battery Last Full